Turning off Std checking in simulation

Discussion in 'VHDL' started by ALuPin@web.de, Jan 16, 2009.

  1. Guest

    Hi newsgroup,

    the following warning at intialization of a simulation

    # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
    operand, the result will be 'X'(es).
    # Time: 0 ns Iteration: 1 Instance: /cordic_tb/uut/add3

    can be avoided by turning off the Std checking in the .do script when
    using Modelsim:

    set StdArithNoWarnings 1
    run 1 ns;
    set StdArithNoWarnings 0
    run 10 ms;

    Does somebody know wheter this technique is available in ActiveHDL ?
    I could not find similar
    set commands.


    Thanks and Rgds
    ALuPin
     
    , Jan 16, 2009
    #1
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  2. Guest

    On Jan 16, 4:32 am, "" <> wrote:
    > Hi newsgroup,
    >
    > the following warning at intialization of a simulation
    >
    >       # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
    > operand, the result will be 'X'(es).
    >       #    Time: 0 ns  Iteration: 1  Instance: /cordic_tb/uut/add3
    >
    > can be avoided by turning off the Std checking in the  .do script when
    > using Modelsim:
    >
    >       set StdArithNoWarnings 1
    >       run 1 ns;
    >       set StdArithNoWarnings 0
    >       run 10 ms;
    >
    > Does somebody know wheter this technique is available in ActiveHDL ?
    > I could not find similar
    > set commands.
    >
    > Thanks and Rgds
    > ALuPin


    To supress ieee warnings you can either use -ieee_nowarn switch with
    asim command, or select something like 'Do not display IEEE warnings'
    in Design->Design Settings->Simulation->VHDL
     
    , Jan 17, 2009
    #2
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  3. Guest

    Thank you for your replies.

    Best Rgds,
    ALuPin
     
    , Jan 22, 2009
    #3
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