Turning off Std checking in simulation

[ALuPin]

Hi newsgroup,

the following warning at intialization of a simulation

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, the result will be 'X'(es).
# Time: 0 ns Iteration: 1 Instance: /cordic_tb/uut/add3

can be avoided by turning off the Std checking in the .do script when
using Modelsim:

set StdArithNoWarnings 1
run 1 ns;
set StdArithNoWarnings 0
run 10 ms;

Does somebody know wheter this technique is available in ActiveHDL ?
I could not find similar
set commands.


Thanks and Rgds
ALuPin

 

[igortsapenko]

Hi newsgroup,

the following warning at intialization of a simulation

      # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
operand, the result will be 'X'(es).
      #    Time: 0 ns  Iteration: 1  Instance: /cordic_tb/uut/add3

can be avoided by turning off the Std checking in the  .do script when
using Modelsim:

      set StdArithNoWarnings 1
      run 1 ns;
      set StdArithNoWarnings 0
      run 10 ms;

Does somebody know wheter this technique is available in ActiveHDL ?
I could not find similar
set commands.

Thanks and Rgds
ALuPin

To supress ieee warnings you can either use -ieee_nowarn switch with
asim command, or select something like 'Do not display IEEE warnings'
in Design->Design Settings->Simulation->VHDL

 

[ALuPin]

Thank you for your replies.

Best Rgds,
ALuPin