Stephane said:
Is there a tutorial anywhere freely available on writing testbecnh files
in VHDL ?
Every testbench is unique and depends on what you want to test. Just
take your "model-under-test" and think about, what should be tested. The
testbench ist that thing, that creates the stimuli, that *you* want for
your model-under-test.
These stimuli can be a sequence of pseudo-random words, a mechanism,
that loads a data file into a modelled RAM-block or whatever ....
Within testbenches you are free to code whatever you want. Don't care
about synthesizeable code, just write something, that creates your
testvectors.
And especially for Quartus 3?
A testbench and especially VHDL itself should (normally) not be written
for a special simulator / synthesizer.
Ralf