Two different `architecture' implementations?

[Merciadri Luca]

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Hi,

I generally write

==
architecture my_arch of my_stuff is
- -- signal, etc., declarations
begin
process
- -- var declarations
begin
- -- code
end process;
end my_arch;
==

but I saw lately, in VHDL Tutorial, by Peter J. Ashenden (Ashenden
designs PTY., LTD., consultant), that he did it this way:

==
architecture my_arch of my_stuff is
- -- signal, etc., declarations
begin
process is
begin
end process;
end architecture my_arch;
==

There are two main differences between our approaches. The first is
that he uses the `is' keyword after `process'. The second is that he
writes `architecture' before the architecture's name, in the closing
line of the architecture my_arch.

Is there a reason to prefer one of the approaches to the other?

Thanks.
- --
Merciadri Luca
See http://www.student.montefiore.ulg.ac.be/~merciadri/
- --

You can fool all of the people some of the time, some of the people all of the time, but you can't fool all of the people all of the time. (Abraham Lincoln)
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[Andy]

Both are optional. I prefer adding "is" after a process statement
(after the sensitivity clause, if present), simply because it makes it
read more like the other vhdl items that have their own declarative
regions.

I also prefer adding the "architecture" keyword after the end
statement, before the name of the architecture, because most "end"
statements have a keyword with them identifying what type of structure
is being ended (end if, end loop, etc.)

But it really boils down to personal preference. I don't mind a little
extra typing for syntactic consistency.

Andy

 

[Merciadri Luca]

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Both are optional. I prefer adding "is" after a process statement
(after the sensitivity clause, if present), simply because it makes it
read more like the other vhdl items that have their own declarative
regions.

I also prefer adding the "architecture" keyword after the end
statement, before the name of the architecture, because most "end"
statements have a keyword with them identifying what type of structure
is being ended (end if, end loop, etc.)

I agree with you on both points.

But it really boils down to personal preference. I don't mind a little
extra typing for syntactic consistency.

You're right. I just thought there was some subtle difference on
another point of view than aesthetic considerations, but apparently
not. Thanks.

- --
Merciadri Luca
See http://www.student.montefiore.ulg.ac.be/~merciadri/
- --

Luck is what happens when preparation meets opportunity. (Lucius Annaeus Seneca)
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[backhus]

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Hi,

I generally write

==
architecture my_arch of my_stuff is
- -- signal, etc., declarations
begin
process
- -- var declarations
begin
- -- code
end process;
end my_arch;
==

but I saw lately, in VHDL Tutorial, by Peter J. Ashenden (Ashenden
designs PTY., LTD., consultant), that he did it this way:

==
architecture my_arch of my_stuff is
- -- signal, etc., declarations
begin
process is
begin
end process;
end architecture my_arch;
==

There are two main differences between our approaches. The first is
that he uses the `is' keyword after `process'. The second is that he
writes `architecture' before the architecture's name, in the closing
line of the architecture my_arch.

Is there a reason to prefer one of the approaches to the other?

Thanks.
- --
Merciadri Luca
Seehttp://www.student.montefiore.ulg.ac.be/~merciadri/
- --

You can fool all of the people some of the time, some of the people all of the time, but you can't fool all of the people all of the time. (Abraham Lincoln)
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Hi Merciadri.
every few years the VHDL standard gets reworked.
Beginning with first release in 1987, then came 1993 which should now
be accepted by all tools.
2002 was next and most of the changes should be available in the
tools.
2008 is the latest change but the tools just started to adopt the new
stuff.

In your simulator there may be a compile switch to select the allowed
standard (e.g. modelsims vcom: -87 -93-2002).
While both of your code examples will pass vcom with the -93 or -2002
option,
I suspect that the second example will fail with the -87 option
enabled.

Just give it a try.
Have a nice simulation
Eilert

 

[Merciadri Luca]

Hi Merciadri.
every few years the VHDL standard gets reworked.
Beginning with first release in 1987, then came 1993 which should now
be accepted by all tools.
2002 was next and most of the changes should be available in the
tools.
2008 is the latest change but the tools just started to adopt the new
stuff.

In your simulator there may be a compile switch to select the allowed
standard (e.g. modelsims vcom: -87 -93-2002).
While both of your code examples will pass vcom with the -93 or -2002
option,
I suspect that the second example will fail with the -87 option
enabled.

Just give it a try.
Have a nice simulation
  Eilert

Thanks for pointing this out.