two related process

Discussion in 'VHDL' started by lucianofalbo, Jul 28, 2008.

  1. lucianofalbo

    lucianofalbo

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    Hi. I have not experience in vhdl but i need to make work this code! It is very important!
    I explain the problem. I have a 24 bits vector as input (B). The input dataready is a signal that is high when B must be read(it is a strobe). I want that the output signal Bup is a 1 microsecond pulse only when B increases. clk50 is a 50 MHz clock. On the contrary these two my processes give 1 microsecond pulses but not always and something also when B does not increase.
    WHY???????Thank you very much for your help

    rst<=dataready;
    gatepr: process (B,dataready,rst)
    variable lastB : std_logic_vector (23 downto 0);
    begin
    if rst='0' then
    up<='0';
    elsif (dataready'event and dataready = '1') then
    if B>lastB then
    up<='1';
    end if;
    Bdiff<=B-lastB;
    lastB:=B;
    end if;
    end process gatepr;

    spero: process(up,clk50)
    variable conta: integer:=51;
    variable last_up: std_logic;
    begin
    if clk50'event and clk50='1' then
    if (up='1' and last_up='0') then
    conta:=0;
    elsif conta<50 then
    Bup<='1';
    elsif conta>=50 then
    Bup<='0';
    end if;
    last_up:=up;
    conta:=conta+1;
    end if;
    end process spero;
    Last edited: Jul 28, 2008
    lucianofalbo, Jul 28, 2008
    #1
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  2. lucianofalbo

    jeppe

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    Not sure - but try this:
    spero: process(up,clk50)
    variable conta: integer:=51;
    variable last_up: std_logic;
    begin
    if clk50'event and clk50='1' then
    if (up='1' and last_up='0') then
    conta:=0;
    end if;
    if conta<50 then
    Bup<='1';
    elsif conta>=50 then
    Bup<='0';
    end if;
    last_up:=up;
    conta:=conta+1;
    end if

    Your welcome
    Jeppe
    jeppe, Jul 29, 2008
    #2
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  3. lucianofalbo

    lucianofalbo

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    Not Work

    DEar Jeppe thanks but your code does not work. I had already tried in that way.
    thanks
    lucianofalbo, Jul 29, 2008
    #3
  4. lucianofalbo

    jeppe

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    Ok one more try - its very hot outside today - better in the shadow

    gatepr: process (B,dataready,rst)
    variable lastB : std_logic_vector (23 downto 0);
    begin
    if rst='0' then
    up<='0';
    elsif (dataready'event and dataready = '1') then
    up<='0'; -- default setting
    if B/=lastB then
    up<='1';
    end if;
    Bdiff<=B-lastB;
    lastB:=B;
    end if;
    end process gatepr;

    Hope this works better
    jeppe, Jul 29, 2008
    #4
  5. lucianofalbo

    lucianofalbo

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    Not Work

    Unfortunately your new code does not work. I am aware that the problem is mainly (only?) in this process (gatepr). The problem with your code and my code is that sometimes I have not the pulse. Furthermore another very strange behaviour is this one: I send a B waveform to the FPGA and after the waveform has finished I continue sending the last value. Then I have pulses during I am sending the last value(B is constant!) . What can be the problem? Maybe the rst I use?
    (I use rst<=dataready outside the process) or the comparation B>lastB?
    All the others elements seem to me very standard things. Or not? what do you think?
    Thanks
    lucianofalbo, Jul 29, 2008
    #5
  6. lucianofalbo

    jeppe

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    Ok - I "cleaned" your code a bit - hopefully will this do the trick :)
    PHP:
    begin
        gatepr
    process (dataready)
            
    variable lastB std_logic_vector (23 downto 0);
        
    begin
            
    if (dataready'event and dataready = '1') then 
                up <= '
    0';
                if B/=lastB then 
                    up <= '
    1';
                end if; 
                Bdiff<=B-lastB;
                lastB:=B; 
            end if; 
        end process gatepr; 

        spero: process(clk50)
            variable conta: integer:=51;
            variable last_up: std_logic;
        begin
            if clk50'
    event and clk50='1' then
                
    if (up='1' and last_up='0'then 
                    conta
    :=0;
                
    end if;
                
    Bup<='0';
                if 
    conta<50 then
                   conta
    :=conta+1;
                   
    Bup<='1';
                
    end if;    
                
    last_up:=up;
            
    end if; 
        
    end process spero;
        
    end Behavioral;
    jeppe, Jul 29, 2008
    #6
  7. lucianofalbo

    lucianofalbo

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    Not Work

    I have used your new code(I have done copy and paste from your post)but it works worst than the others: I have only few pulses and not always in the same positions. :-(
    Thanks for your past and future attempts.
    lucianofalbo, Jul 29, 2008
    #7
  8. lucianofalbo

    jeppe

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    Well well - have you tried to make a sketch of the signals your planningto messure.

    You must consider how often the dataready changes etc.
    May be its not possible to do, what your want to do.

    Some of the signals you generates with the two processes could may be better be incorperated "closer" to the "B" counter.

    A simulation (with downscaled clk signals etc) could give you some hints but still if your problems "noise" will a simulation not help you.

    A hard one indeed :-(
    jeppe, Jul 29, 2008
    #8
  9. lucianofalbo

    lucianofalbo

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    why?

    Dataready is 300 kHz signal that is high for about 1.6 microsecond. It becomes high about 10 nsec the new B is ready. clk50 is a 50 MHz signal. Why do you think this could be a problem?
    lucianofalbo, Jul 29, 2008
    #9
  10. lucianofalbo

    jeppe

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    My final solution - I believe a single FSM must be the best way to avoid timing, glitches or what ever the "real" problem.

    PHP:
    entity FSM_solution1 is
        Port 
    Clk50MHz :  in  STD_LOGIC;
               
    Reset :     in  STD_LOGIC;
               
    Dataready in  STD_LOGIC;
               
    :         in  STD_LOGIC_VECTOR (23 downto 0);
               
    Bup :       out  STD_LOGIC);
    end FSM_solution1;

    architecture Behavioral of FSM_solution1 is
        type   States is 
    (Detect_Dataready0,Detect_Dataready1Test_BMake_Bup_Puls);
        
    signal State:   States;
        
    signal Counterinteger range 0 to 63;
        
    signal Last_B:  STD_LOGIC_VECTOR (23 downto 0); 
        
    begin
        process
    Clk50MHz)
        
    begin
            
    if rising_edgeClk50MHzthen
                
    if Reset='1' then
                    State  
    <= Detect_Dataready0;
                    
    Bup    <= '0';
                    
    Last_B <= B;
                else
                    case 
    State is
                        when Detect_Dataready0 
    =>
                            
    Bup <= '0';
                            if 
    Dataready='0' then
                                State 
    <= Detect_Dataready1;
                            
    end if;
                        
    when Detect_Dataready1 =>
                            
    Bup <= '0';
                            if 
    Dataready='1' then
                                State 
    <= Test_B;
                            
    end if;
                        
    when Test_B =>
                            
    Bup <= '0';    
                            if 
    B/=Last_B then
                                Counter 
    <= 1;
                                
    State <= Make_Bup_Puls;
                            else
                                
    State <= Detect_Dataready0;
                            
    end if;
                            
    Last_B <= B;
                        
    when Make_Bup_Puls =>
                            
    Counter <= Counter+1;
                            
    Bup <= '1';
                            if 
    Counter 49 then
                                State   
    <= Detect_Dataready0
                            
    end if;
                    
    end case;
                
    end if;
            
    end if;
        
    end process;
    end Behavioral;
    Your welcome
    Jeppe
    Last edited: Jul 30, 2008
    jeppe, Jul 30, 2008
    #10
  11. lucianofalbo

    jeppe

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    Well I got one try - if the former miss:

    PHP:
    entity FSM_Soultion2 is
        Port 
    Clk50MHz :  in  STD_LOGIC;
               
    Reset :     in  STD_LOGIC;
               
    Dataready in  STD_LOGIC;
               
    :         in  STD_LOGIC_VECTOR (23 downto 0);
               
    Bup :       out  STD_LOGIC);
    end FSM_Soultion2;

    architecture Behavioral of FSM_Soultion2 is
        type   States is 
    (Detect_Dataready0,Detect_Dataready1Test_BMake_Bup_Puls);
        
    signal State:   States;
        
    signal Counterinteger range 0 to 63;
        
    signal Last_BSTD_LOGIC_VECTOR (23 downto 0);
        
    Signal Sync_DatareadySTD_LOGIC;     
        
    begin
        Sync
    processClk50MHz)
        
    begin
            
    if rising_edgeClk50MHzthen
                Sync_Dataready 
    <= Dataready; -- To make sure this signal synchronized
            end 
    if;
        
    end process Sync;

        
    FSMprocessClk50MHz)
        
    begin
            
    if rising_edgeClk50MHzthen
                
    if Reset='1' then
                    State  
    <= Detect_Dataready0;
                    
    Bup    <= '0';
                    
    Last_B <= B;
                else
                    case 
    State is
                        when Detect_Dataready0 
    =>
                            
    Bup <= '0';
                            if 
    Sync_Dataready='0' then
                                State 
    <= Detect_Dataready1;
                            
    end if;
                        
    when Detect_Dataready1 =>
                            
    Bup <= '0';
                            if 
    Sync_Dataready='1' then
                                State 
    <= Test_B;
                            
    end if;
                        
    when Test_B =>
                            
    Bup <= '0';    
                            if 
    B/=Last_B and Sync_Dataready='1' then
                                Counter 
    <= 1;
                                
    State <= Make_Bup_Puls;
                            else
                                
    State <= Detect_Dataready0;
                            
    end if;
                            
    Last_B <= B;
                        
    when Make_Bup_Puls =>
                            
    Counter <= Counter+1;
                            
    Bup <= '1';
                            if 
    Counter 49 then
                                State   
    <= Detect_Dataready0
                            
    end if;
                    
    end case;
                
    end if;
            
    end if;
        
    end process FSM;
    end Behavioral;
    jeppe, Jul 30, 2008
    #11
  12. lucianofalbo

    lucianofalbo

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    great problems

    Thanks for your FSM code, I will try it. I have not tried it because I have found another problem in another process of the same entity. Maybe the problem source is the same. I am worried because the process is VERY simple:

    B_enable : process (dataready,B)
    variable Bmin: std_logic_vector (23 downto 0);
    variable Bmax: std_logic_vector (23 downto 0);
    begin
    Bmin := "000011001010101111110011";
    Bmax := "000011011001110110010001";
    if dataready'event and dataready = '1' then
    if ( B > Bmin and B<Bmax ) then
    Benable <= '1';
    else
    Benable <= '0';
    end if;
    end if;
    end process B_enable;

    The problem is that this process generates a 40 nsec pulse when there is no no reason that Benable becomes high. What do you think? A problem in the xilinx board (spartan3)???
    lucianofalbo, Jul 31, 2008
    #12
  13. lucianofalbo

    lucianofalbo

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    thanks jeppe

    Thank you very very much for your FSM. I have tried the first one and it seems it works! Wonderfull! You are great! And what about the process of my last post? Also in that case is it better to use a FSM? (up to yesterday I did not know what a FSM was). What do you think? thanks again for your help
    lucianofalbo, Jul 31, 2008
    #13
  14. lucianofalbo

    jeppe

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    Good to hear about your succes - wonder if if the DataReady signal is asyncrone to the system clock - could be an explanation to your problem and the the trick will be the Syncronization F/F (read process)
    This also true for your later process.

    You could perhaps include this part in the FSM where B /= Last_B or make a new FSM with say two states.

    Jeppe
    Last edited: Jul 31, 2008
    jeppe, Jul 31, 2008
    #14
  15. lucianofalbo

    lucianofalbo

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    really the problem is again here

    DEar Jeppe
    I have written the FSM for the other process (Benable); unfortunately I have found a bug in the new process and thanks to this bug I have found a bug in the FSM codes you have sent me. (I have checked with only your code so there is not a problem of interaction between the two FSM). I have tried with both of the codes you sent me and the problem is the same. First of all I have to say you that I have had to replace the instruction

    if B /= Last_B then

    with the instruction

    if B > Last_B then

    because I want to see if B increases not if B changes.
    So, even if generally the process works, the problem is that during a time of 100 msec in which B is DEcreasing I have a Bup pulse of 1 microsecond. The pulse is when B goes from
    "1100100000000000000" to
    "1100011111111111111".
    In the same time, when I insert the Benable FSM that generally works, I have a Benable pulse of 3 microsecond even if I am far from the condition
    B>"000011001010101111110011" and B<"000011011001110110010001" of the Benable FSM.
    What do you think? The problem is the operator >?
    bye
    lucianofalbo, Aug 1, 2008
    #15
  16. lucianofalbo

    jeppe

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    Hi
    Off course should you use the > operator if your only interested to detect an increment of B.

    The REAL problem in a design like yours will be signals which changes asyncronous with the system clock (50 MHz)

    When a 24-bit vector like B changes can't you be sure that all bit changes instantly -
    example with 3-bit vector 101 -> 111 -> 110

    The Last_B gives you no problem as its value held by 24 F/F's
    If you write your like this:
    New_B <= B;
    Last_B <= New_B

    and the compare New_B > Last_B should this problem be solved.

    Jeppe
    Last edited: Aug 1, 2008
    jeppe, Aug 1, 2008
    #16
  17. lucianofalbo

    lucianofalbo

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    tests not ok

    Considering what happens I think you are really right! Howevere maybe I have not understood your suggestions. I have tried two ways without success.
    I report here your FSM with the changes labelled with *************** so you can say me what you meant and you see what does not work.(thanks again)
    1) if rising_edge( clk50) then
    if Reset='1' then
    State <= Detect_Dataready0;
    Bup <= '0';
    NewB <= B; ******************
    Last_B <= NewB; ******************
    else
    case State is
    when Detect_Dataready0 =>
    Bup <= '0';
    if Sync_Dataready='0' then
    State <= Detect_Dataready1;
    end if;
    when Detect_Dataready1 =>
    Bup <= '0';
    if Sync_Dataready='1' then
    State <= Test_B;
    end if;
    when Test_B =>
    Bup <= '0';
    if NewB > Last_B then ************************
    Counter <= 1;
    State <= Make_Bup_Puls;
    else
    State <= Detect_Dataready0;
    end if;
    NewB<=B; **************************
    Last_B <= NewB; ************************
    when Make_Bup_Puls =>
    Counter <= Counter+1;
    Bup <= '1';
    if Counter > 49 then
    State <= Detect_Dataready0;
    end if;
    end case;
    end if;
    end if;
    2) if rising_edge( clk50) then
    if Reset='1' then
    State <= Detect_Dataready0;
    Bup <= '0';
    NewB <= B;
    Last_B <= NewB;
    else
    case State is
    when Detect_Dataready0 =>
    Bup <= '0';
    if Sync_Dataready='0' then
    State <= Detect_Dataready1;
    end if;
    when Detect_Dataready1 =>
    Bup <= '0';
    if Sync_Dataready='1' then
    NewB<=B; ****************************
    State <= Test_B;
    end if;
    when Test_B =>
    Bup <= '0';
    if NewB > Last_B then ***********************
    Counter <= 1;
    State <= Make_Bup_Puls;
    else
    State <= Detect_Dataready0;
    end if;
    Last_B <= NewB; **************************
    when Make_Bup_Puls =>
    Counter <= Counter+1;
    Bup <= '1';
    if Counter > 49 then
    State <= Detect_Dataready0;
    end if;
    end case;
    end if;
    end if;
    lucianofalbo, Aug 1, 2008
    #17
  18. lucianofalbo

    jeppe

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    Hi Again - try to Go Advanced and use the PHP to preserve tabs of the sourcetext.

    The syncronization should be held in a separate process (I forgot)
    Wonder which clock signal / frequency used to update B.

    Jeppe

    PHP:
    entity Test2 is
        Port 
    Clk50 :       in   STD_LOGIC;
               
    Reset :       in   STD_LOGIC;
               
    DataReady :   in   STD_LOGIC;
               
    :           in   STD_LOGIC_VECTOR (23 downto 0);
               
    BupBenable :out  STD_LOGIC);
    end Test2;

    architecture Behavioral of Test2 is
        type       States is 
    (Detect_Dataready0,Detect_Dataready1Test_BMake_Bup_Puls); 
        
    signal     State:   States
        
    signal     Counterinteger range 0 to 63
        
    signal     NewB,Last_B:    STD_LOGIC_VECTOR (23 downto 0);
        
    signal   Sync_B:         STD_LOGIC_VECTOR (23 downto 0);  
        
    signal     Sync_DataReadySTD_LOGIC;
        
    constant Bminstd_logic_vector (23 downto 0) := "000011001010101111110011";
        
    constant Bmaxstd_logic_vector (23 downto 0) := "000011011001110110010001"
        
    begin
       
        Syncronize
    processClk50)  -- THIS PROCESS TOO MAKE EVENTUALLY ASCYNCRONE SIGNALSSYNCRONE WITH Clk50
        begin
            
    if Rising_edge(Clk50then
                Sync_B            
    <= B;
                
    Sync_DataReady <= DataReady;
            
    end if;
        
    end process Syncronize;
        
        
    FSMprocessClk50)
        
    begin
            
    if rising_edgeclk50then
                
    if Reset='1' then
                    State  
    <= Detect_Dataready0;
                    
    Bup    <= '0';
                else
                    case 
    State is
                    when Detect_Dataready0 
    =>
                        
    Bup <= '0';
                        if 
    Sync_Dataready='0' then
                            State 
    <= Detect_Dataready1;
                        
    end if;
                    
    when Detect_Dataready1 =>
                        
    Bup <= '0';
                        if 
    Sync_Dataready='1' then
                           NewB   
    <= Sync_B;
                            
    Last_B <= NewB;
                            
    State  <= Test_B;
                        
    end if;
                    
    when Test_B =>
                        ------------------------------------------------------
                        if ( 
    NewB Bmin and NewB<Bmax then
                            Benable 
    <= '1';
                        else 
                            
    Benable <= '0';
                        
    end if;
                        -------------------------------------------------------
                        
    Bup <= '0'
                        if 
    NewB Last_B then 
                            Counter 
    <= 1;
                            
    State   <= Make_Bup_Puls;
                        else
                            
    State <= Detect_Dataready0;
                        
    end if;
                    
    when Make_Bup_Puls =>
                        
    Counter <= Counter+1;
                        
    Bup <= '1';
                        if 
    Counter 49 then
                            State 
    <= Detect_Dataready0
                        
    end if;
                    
    end case;
                
    end if;
           
    end if;
       
    end process FSM;
        
    end Behavioral;
    Last edited: Aug 2, 2008
    jeppe, Aug 1, 2008
    #18
  19. lucianofalbo

    lucianofalbo

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    Not Work

    Hi
    Unfortunately also with your new changes the code has again the same problem
    (for Bup and Benable).
    Any other suggestions?
    thanks
    lucianofalbo, Aug 4, 2008
    #19
  20. lucianofalbo

    jeppe

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    Have you noticed the code @ #18 been updated.
    I wonder how often the vector B actually changes. May be could you solve the problem with the following "trick"

    PHP:
    process (ClkB) -- [I]Wonder which Clock updates B called it ClkB[/I]
    begin
        
    if rising_edge(ClkBthen
             B 
    <= B+1;
        
    end if;

         if 
    falling_edge(ClkBthen
             Sync_B 
    <= B;  -- Hopefully will the Sync_B vector be stable
         end 
    if;
    end process;
    jeppe, Aug 4, 2008
    #20
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