.txt files as testbench

[Dek]

Hi everybody,

I'm trying to simulate the behavior of an hardware design using as
testbench data already stored in .txt files. In another thread Mike
Treseler suggest me to do so:

I prefer to convert existing text files to vhdl packages
using a scripting language, since I am using one anyway
to run modelsim.

Now I would really like to try this way, but I have no idea of how to
do that; in particular, do you have any exemple of packages containing
data to be used for testbench? Sorry for the newbie question, but I
have just started with VHDL.

Thanks

Bye

Dek


P.S. I already post this question, but since it was more focused on
using TextIO I thought to create a new thread; I hope this doesn't
bother anyone

 

[goouse]

Hi everybody,

I'm trying to simulate the behavior of an hardware design using as
testbench data already stored in .txt files. In another thread Mike
Treseler suggest me to do so:

I prefer to convert existing text files to vhdl packages
using a scripting language, since I am using one anyway
to run modelsim.

Now I would really like to try this way, but I have no idea of how to
do that; in particular, do you have any exemple of packages containing
data to be used for testbench? Sorry for the newbie question, but I
have just started with VHDL.

Thanks

Bye

Dek

P.S. I already post this question, but since it was more focused on
using TextIO I thought to create a new thread; I hope this doesn't
bother anyone

Hi Dek,
matlab uses this approach for generating testbenches.
The test vectors there are derived from a simulink environment, but
the vectors are written to a (large) array and fed to the DUT.
The feeding procedure and the test vector array are part of a package
that is generated by the matlab tools (generatetb).

But writing some functions/procedures/processes that read the vectors
directly from a text file is simpler and much more straight forward.
There is an opencores project that may be helpful for your purpose:
http://www.opencores.org/?do=project&who=vhld_tb

Have a nice simulation
Eilert

 

[Mike Treseler]

do you have any exemple of packages containing
data to be used for testbench?

Here is an example vector array constant
that could be used by a testbench.

In simple cases,
I might use a editor macro
rather than a script to
convert the raw text file.

-- Mike Treseler

___________________________________
library ieee;
use ieee.std_logic_1164.all;

package my_pkg is
constant data_length : natural := 16;
constant add_length : natural := 10;
constant mem_size : natural := 2**add_length;
type mem_type is array (mem_size-1 downto 0) of
std_logic_vector (data_length-1 downto 0);

constant mem : mem_type := (
0 => x"abcd",
1 => x"beef",
2 => x"5555",
3 => x"1010",
4 => x"5a6b",
5 => x"f0f0",
6 => x"1234",
7 => x"fabc",
8 => x"2345",
9 => x"9876",
10 => x"5432",
11 => x"6666",
12 => x"0101",
13 => x"abab",
others => x"4247");

end package my_pkg;