type casting vs. type converting

Discussion in 'VHDL' started by Toby, Sep 7, 2005.

  1. Toby

    Toby Guest

    type casting vs. type converting... what is the difference? which is
    better? any examples would be helpful.
    Toby, Sep 7, 2005
    #1
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  2. Toby

    Toby Guest

    more specifically i am interested in changing between std_logic_vectors
    and signed and unsigned types (i.e. from std_logic_vector to unsigned
    and from unsigned to std_logic_vector). there doesnt seem to be any
    to_unsigned(std_logic_vector) function in the numeric_std library, why
    is that? is there any way around that?
    Toby, Sep 7, 2005
    #2
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  3. Toby

    Ben Jones Guest

    Hi Toby,

    > there doesnt seem to be any to_unsigned(std_logic_vector) function
    > in the numeric_std library, why is that? is there any way around that?


    The numeric_std "signed" and "unsigned" types are defined exactly like the
    type "std_logic_vector" is defined in std_logic_1164 - they are all arrays
    with elements of type std_logic. This makes them what VHDL calls "related"
    types, which can easily be convered between. For example:

    signal x,y : std_logic_vector(7 downto 0);
    signal a,b : unsigned(7 downto 0);

    x <= std_logic_vector(a);
    b <= unsigned(y);

    -Ben-
    Ben Jones, Sep 7, 2005
    #3
  4. Toby wrote:
    > more specifically i am interested in changing between std_logic_vectors
    > and signed and unsigned types (i.e. from std_logic_vector to unsigned
    > and from unsigned to std_logic_vector). there doesnt seem to be any
    > to_unsigned(std_logic_vector) function in the numeric_std library, why
    > is that? is there any way around that?
    >


    http://groups.google.com/groups?q=vhdl std_logic_vector closely related type

    -- Mike Treseler
    Mike Treseler, Sep 7, 2005
    #4
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