type conversion problem

Discussion in 'VHDL' started by mahmoud, Sep 4, 2008.

  1. mahmoud

    mahmoud

    Joined:
    Sep 4, 2008
    Messages:
    2
    hi all,
    i am trying to do a simple code using vhdl but the problem presists...i am trying to add a std_logic_vector type elements and i wrote the following

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity test is
    port (
    NBC :in std_logic_vector(3 downto 0);
    op :eek:ut std_logic_vector(2 downto 0)
    );
    end test;
    architecture arch of test is
    signal sum :unsigned (2 downto 0);
    begin

    sum <=unsigned(std_logic_vector("00"&NBC(0)))+unsigned(std_logic_vector("00"&NBC(1)))+unsigned(std_logic_vector("00"&NBC(2)))+unsigned(std_logic_vector("00"&NBC(3)));

    op <=std_logic_vector(sum);

    end arch;

    plz i wanna know where is the problem ........thanks for help
    mahmoud, Sep 4, 2008
    #1
    1. Advertising

  2. mahmoud

    Steff

    Joined:
    Sep 8, 2008
    Messages:
    11
    Hi,

    if you have typeless vector like "00" and you want to convert it to a concret type you have to do it in the following way:

    type'("00")

    sum <= unsigned'("00"&NBC(0))+
    unsigned'("00"&NBC(1))+
    unsigned'("00"&NBC(2))+
    unsigned'("00"&NBC(3));

    But for your case it is easier to do it this way:

    sum <= "00"&NBC(0)+"00"&NBC(1)+"00"&NBC(2)+"00"&NBC(3);


    Hope I could help you! :)

    Bye, Steff
    Last edited: Sep 15, 2008
    Steff, Sep 8, 2008
    #2
    1. Advertising

  3. mahmoud

    mahmoud

    Joined:
    Sep 4, 2008
    Messages:
    2
    hi steff,

    ur attempt to help is greatly appreciated ....i have tried the line u just has edited now :

    sum <= "00"&NBC(0)+"00"&NBC(1)+"00"&NBC(2)+"00"&NBC(3 );

    but after introducing a new intermediate signal ...>>>
    i wrote the code as follows:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    entity test is
    port (
    NBC :in std_logic_vector(3 downto 0);
    op :eek:ut std_logic_vector(2 downto 0)
    );
    end test;
    architecture arch of test is
    signal sum :unsigned (2 downto 0);
    signal sum_un :unsigned(3 downto 0);

    begin
    sum_un<=unsigned(NBC);
    sum <= ("00"&sum_un(0))+
    ("00"&sum_un(1))+
    ("00"&sum_un(2))+
    ("00"&sum_un(3 ));

    op <= std_logic_vector(sum);
    end arch;

    Also i have tried to remove this signal ....as u suggested and it worked....i dont know the impact on the synthesis but i'll discover soon ..
    thanks for ur help steff :)

    bye
    Last edited: Sep 8, 2008
    mahmoud, Sep 8, 2008
    #3
  4. mahmoud

    Steff

    Joined:
    Sep 8, 2008
    Messages:
    11
    Your welcome!
    Steff, Sep 8, 2008
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. luna
    Replies:
    1
    Views:
    6,802
  2. ibiza
    Replies:
    2
    Views:
    5,328
    ibiza
    Jan 27, 2006
  3. Chris
    Replies:
    2
    Views:
    21,322
    Chris
    May 11, 2006
  4. Michal Nazarewicz

    conversion from const type* to type* allowed?

    Michal Nazarewicz, Jan 4, 2007, in forum: C Programming
    Replies:
    13
    Views:
    550
    Eric Sosman
    Jan 5, 2007
  5. zaeminkr@gmail.com
    Replies:
    1
    Views:
    441
    Sylvester Hesp
    May 16, 2007
Loading...

Share This Page