type convertion of an unconstrained output in a port map

[ygrugni]

Can sombody tell me if the code below is vhdl 93 compliant or not.
Most of the compilers doesn't accept it but this doesn't mean that is
not vhdl 93 compliant.
Ncvhdl/ncsim (from cadence) for example accept it.
The problem of this code is that a type convertion is performed on an
unconstrained output in a port map,
I don't know if it's correct or not.

------------------------------------------------------
-- file add_unconstrained.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY add_unconstrained IS
PORT (
sample_in1 : IN unsigned;
sample_in2 : IN unsigned;
sample_out : OUT unsigned
);
END add_unconstrained;

ARCHITECTURE rtl OF add_unconstrained IS
BEGIN

sample_out <= sample_in1 + sample_in2;

END rtl;

------------------------------------------------------
-- file type_conversion_of_unconstr_output.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


ENTITY type_conversion_of_unconstr_output IS
PORT (
Asample_in1 : IN std_logic_vector(7 DOWNTO 0);
Asample_in2 : IN std_logic_vector(7 DOWNTO 0);
Asample_out : OUT std_logic_vector(7 DOWNTO 0)
);
END type_conversion_of_unconstr_output;

ARCHITECTURE rtl OF type_conversion_of_unconstr_output IS

COMPONENT add_unconstrained
PORT (
sample_in1 : IN unsigned;
sample_in2 : IN unsigned;
sample_out : OUT unsigned
);
END COMPONENT;

SIGNAL Asample_in1_tmp : unsigned(7 DOWNTO 0);
SIGNAL Asample_in2_tmp : unsigned(7 DOWNTO 0);

BEGIN
Asample_in1_tmp <= unsigned(Asample_in1);
Asample_in2_tmp <= unsigned(Asample_in2);

u_add : add_unconstrained
PORT MAP (
sample_in1 => Asample_in1_tmp,
sample_in2 => Asample_in2_tmp,
std_logic_vector(sample_out) => Asample_out -- ??? IS this line
vhdl 93 compliant ???
);

END rtl;

 

[Neo]

I dont know what vhdl-93 has to do with it but its not possible. There
is no indication of how many bits and which to assign to sample_out.

 

[Jonathan Bromley]

I dont know what vhdl-93 has to do with it

VHDL-93 fixed an oversight in VHDL-87...
* '87 allowed a function with a single argument to appear
in a port map
* '93 very sensibly extended that to permit an array type
conversion, which looks and behaves rather like a
function call

but its not possible. There is no indication of how
many bits and which to assign to sample_out.

I agree that the LRM appears to forbid this, in
section 3.2.1.1.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

I agree that the LRM appears to forbid this, in
section 3.2.1.1.

Modelsim agrees.
It compiles fine, but elaboration is impossible.

-- Mike Treseler
______________________
65 steptoe Tue Feb 08 > vcom -93 unconstrained.vhd
65 steptoe Tue Feb 08 > vsim -c add_unconstrained
Reading /steptoe/usr1/modeltech/tcl/vsim/pref.tcl
# 5.8c
# vsim -c add_unconstrained
# // ModelSim SE 5.8c Mar 01 2004 Linux 2.6.8-24.10-default
# Loading /steptoe/usr1/modeltech/linux/../std.standard
# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /steptoe/usr1/modeltech/linux/../ieee.numeric_std(body)
# Loading work.add_unconstrained(rtl)
# ** Fatal: (vsim-3347) Port 'sample_in1' is not constrained.
# Time: 0 ns Iteration: 0 Instance: /add_unconstrained File:
/evtfs/home/tres/vhdl/play/unconstr.vhd
# FATAL ERROR while loading design
# Error loading design
Error loading design

 

[Srinivasan Venkataramanan]

Mike,
Though your observation may be correct (not sure, please refer to my
other reply as well), you might have wanted to run "vsim
type_conversion_of_unconstr_output " than on the unconstrained entity.

Disclaimer: I'm not a regular VHDL user for some time now and hence my VHDL
knowledge is surely *rusted* - I feel sorry, but can't help it.

Thanks,
Sri

--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned

 

[Srinivasan Venkataramanan]

Hi,
Let me start with the disclaimer that my VHDL know-how is *rusted* and am
trying to understand this better.

From LRM, 3.2.1.1, I find closest matching text as (slightly edited):
------- LRM
For a formal port of a design entity that is of an unconstrained array type
and that is associated in whole, the index ranges are obtained from the
corresponding association element in the port map aspect of the applicable
(implicit or explicit) binding indication.

-------- LRM

So I wonder why "sample_out" (formal) can't derive its range from
"Asample_out : OUT std_logic_vector(7 DOWNTO 0)" - the actual.

It is also puzzling to me that the same works for the "sample_in1" (and 2).

To me it looks like it is legal!

Thanks,
Sri


--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned

 

[Neo]

I thought vectors were not treated as arrays. anyway the approach below
gets over it.
with changes as below (Asample_out_tmp is a signal declared as
unsigned).
sample_in1 => Asample_in1_tmp,
sample_in2 => Asample_in2_tmp,
sample_out => Asample_out_tmp
--std_logic_vector(sample_out),
);
Asample_out <= std_logic_vector(Asample_out_tmp);

 

[Egbert Molenkamp]

I thought vectors were not treated as arrays. anyway the approach below
gets over it.
with changes as below (Asample_out_tmp is a signal declared as
unsigned).
sample_in1 => Asample_in1_tmp,
sample_in2 => Asample_in2_tmp,
sample_out => Asample_out_tmp
--std_logic_vector(sample_out),
);
Asample_out <= std_logic_vector(Asample_out_tmp);

You could also add a generic in de entity declaration of "add_unconstrained"
In case it should be VHDL'87 compatible simple functions can embed the type
conversion functions.

Egbert Molenkamp

COMPONENT add_unconstrained
GENERIC (w : integer);
PORT (
sample_in1 : IN unsigned;
sample_in2 : IN unsigned;
sample_out : OUT unsigned (w-1 downto 0)
);
END COMPONENT;

FUNCTION to_stdlogicvector (i : unsigned) RETURN std_logic_vector IS
BEGIN
RETURN std_logic_vector(i);
END to_stdlogicvector;

FUNCTION to_unsigned (i : std_logic_vector) RETURN unsigned IS
BEGIN
RETURN unsigned(i);
END to_unsigned;

BEGIN

u_add_VHDL93 : add_unconstrained
GENERIC MAP(w=> Asample_out'LENGTH)
PORT MAP (
sample_in1 => unsigned(Asample_in1),
sample_in2 => unsigned(Asample_in2),
std_logic_vector(sample_out) => Asample_out
);

u_add_VHDL87_VHDL93 : add_unconstrained
GENERIC MAP(w=> Asample_out'LENGTH)
PORT MAP (
sample_in1 => to_unsigned(Asample_in1),
sample_in2 => to_unsigned(Asample_in2),
to_stdlogicvector(sample_out) => Asample_out
-- to_stdlogicvector is located in std_logic_1164
);

 

[Mike Treseler]

Though your observation may be correct (not sure, please refer to my
other reply as well), you might have wanted to run "vsim
type_conversion_of_unconstr_output " than on the unconstrained entity.

Good point, let's try it:

61 steptoe Thu Feb 10 /evtfs/home/tres/vhdl/play > !60
vsim -c type_conversion_of_unconstr_output
Reading /steptoe/usr1/modeltech/tcl/vsim/pref.tcl
# 5.8c
# vsim -c type_conversion_of_unconstr_output
# // ModelSim SE 5.8c Mar 01 2004 Linux 2.6.8-24.10-default
# Loading /steptoe/usr1/modeltech/linux/../std.standard
# Loading /steptoe/usr1/modeltech/linux/../ieee.std_logic_1164(body)
# Loading /steptoe/usr1/modeltech/linux/../ieee.numeric_std(body)
# Loading work.type_conversion_of_unconstr_output(rtl)
# Loading work.add_unconstrained(rtl)
# ** Fatal: (vsim-3346) Output port 'sample_out' is not constrained.
# Time: 0 ns Iteration: 0 Instance:
/type_conversion_of_unconstr_output/u_add File:
/evtfs/home/tres/vhdl/play/add_unconstrained.vhd
# FATAL ERROR while loading design