Type declarations

Discussion in 'VHDL' started by FPGA, Jan 23, 2008.

  1. FPGA

    FPGA Guest

    I am trying to use the following function defined in the ieee_proposed
    library

    -- to_signed (float)
    function to_signed (
    arg : UNRESOLVED_float; -- floating point input
    constant size : NATURAL; -- length of output
    constant check_error : BOOLEAN := float_check_error; -- check
    for errors
    constant round_style : round_type := float_round_style) --
    rounding option
    return SIGNED is

    I want to test this function. I have given inputs to entity as below

    float_in : in std_logic_vector(31 downto 0);
    signed_out : out std_logic_vector(63 DOWNTO 0);

    I want to try

    signed_out <= to_signed(float_in);

    Note that the input(arg) to the function to_signed is of type
    UNRESOLVED_float. How do i convert this to std_logic_vector.
    If i mention the float_in input of type UNRESOLVED_float, it gives me
    error : "Unknown identifier: UNRESOLVD_float". This is the same
    problem i am having with some of the other functions I am trying to
    test.
    The type declarations are in the architecture body and NOT BEFORE THE
    DECLARATION OF THE ENTITY. How do i fix this problem?


    Complete function definition ca be found here
    http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/float_pkg_c.vhdl

    Thanks
    FPGA, Jan 23, 2008
    #1
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