u in web pack

Discussion in 'VHDL' started by efemero06, Jul 6, 2006.

  1. efemero06

    efemero06

    Joined:
    Jul 6, 2006
    Messages:
    1
    Hi everybody

    I am a begginer programer in vhdl, and i am working in my final work of college, so i am tryng to build a shift register with asynchronous reset. the reset signal is created by a combinational circuito and resets all flipflops D.

    But when I simulate in webpack of xilinx i get a waveform with a constant red line with "u".

    I've reserched and found that it means that is uninitialized.

    Please , help me I am not undestanding it, why this "u" appears, and how i can eliminate it and simulate normaly my circuit.

    Thank you

    Below i've posted my source code:

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity delay1 is
    Port ( clk : in std_logic;
    ams2 : in std_logic;
    ams3 : in std_logic;
    awe: in std_logic;
    are : in std_logic;
    aredly : out std_logic;
    awedly: out std_logic;
    set : in std_logic);
    end delay1;

    architecture Behavioral of delay1 is
    component ffdrs
    port(clk, d, rst, set: in std_logic; q:eek:ut std_logic);
    end component;
    signal s1, s2, s3, s4, s5, s6, s7, s8, s9, rst: std_logic;
    begin

    --------------------------------------------------------
    --CIRCUITOS PARA ACIONAMENTO DE RESET ASSINCRONO
    ---------------------------------------------------------

    s1<=(not ams2)and(not ams3);
    s2<=(not awe)and(not are);
    s3<=s2 or s1;
    rst<=s1;

    ---------------------------------------------------------
    --FLIP FLOPS PARA ATRASO DO SINAL DE LEITURA
    --ATRASO DE 3 CICLOS DE CLOCK
    ---------------------------------------------------------

    ffdr1: ffdrs port map(clk=>clk, d=>are, rst=>rst, set=>set, q=>s4);
    ffdr2: ffdrs port map(clk=>clk, d=>s4, rst=>rst, set=>set, q=>s5);
    ffdr3: ffdrs port map(clk=>clk, d=>s5, rst=>rst, set=>set, q=>aredly);

    ----------------------------------------------------------
    --FLIP FLOPS PARA ATRASO DO SINAL DE ESCRITA
    --ATRASO DE 3 CICLOS DE CLOCK
    ----------------------------------------------------------

    ffdr4: ffdrs port map(clk=>clk, d=>awe, rst=>rst, set=>set, q=>s6);
    ffdr5: ffdrs port map(clk=>clk, d=>s6, rst=>rst, set=>set, q=>s7);
    ffdr6: ffdrs port map(clk=>clk, d=>s7, rst=>rst, set=>set, q=>awedly);
    ----------------------------------------------------------

    end Behavioral;

    the source for the flip flop D is below too

    entity ffdrs is
    Port ( clk : in std_logic;
    rst : in std_logic;
    set : in std_logic;
    d : in std_logic;
    q : out std_logic);
    end ffdrs;

    architecture Behavioral of ffdrs is

    begin
    process (clk, rst, set) is
    begin
    if (rst= '1') then q <='0';
    elsif(set='1') then q <='1';
    elsif( clk'event and clk='1') then q <= d;
    end if;
    end process;
    end Behavioral;
    efemero06, Jul 6, 2006
    #1
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