On Tue, 03 Oct 2006 20:03:30 +0200, Nicolas Matringe
[...]
This comes from the default direction being TO. It's the same for any
array. Define a constant like this :
constant C_FOO : std_logic_vector := x"132";
and it will have an ascending range (0 to 11 in this case).
The discussion with my colleague was exactly about that : how to have a
std_logic_vector constant that would default to a descending range.
It is tedious that VHDL doesn't have modified versions of the
unconstrained array type declaration, something like this:
type descending_slv is array (natural range >) of std_logic;
type ascending_slv is array (natural range <) of std_logic;
which would enforce the subscript direction. On the other hand,
it's easy to re-arrange the subscript direction inside your own
code, particularly in a function or procedure:
function F(V: std_logic_vector) return ... is
subtype T_descending is std_logic_vector(V'high downto V'low);
constant V_descending: T_descending := V;
begin
...
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