Unconstrained array for output port in generic :/

[killerhertz]

I'm fairly new to generics, consequently I'm having problems

I'm trying to create an entity with 'width' bits in and 'nbits'x'width'
bits out. I'm trying to use an unconstrained array to do this, but I'm
getting compile errors...

# ** Error: C:/Modeltech_6.0c/work/srsipo.vhd(34): near "array":
expecting: STRING IDENTIFIER

Any ideas? Thanks.

-Brandon

<SNIP>

library ieee;
use ieee.std_logic_1164.all;
use work.srsipo_pkg.all;

-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity srsipo is
generic (
nbits : integer;
width : integer
);
port (

 

[Ralf Hildebrandt]

I'm trying to create an entity with 'width' bits in and 'nbits'x'width'
bits out. I'm trying to use an unconstrained array to do this, but I'm
getting compile errors...

entity srsipo is
generic (
nbits : integer;
width : integer
);
port (

---------------------------------------------------------------------------
-- input
------------------------------------------------------------------
rst_na : in std_logic;
clk : in std_logic;
din : in std_logic_vector(width-1 downto 0);
-- output

You have to define a type, that will be used for dout. At the moment,
you try to define a type AND use it at the same time. The type should be
defined in a package.



Remember: Old synthesis tools may not support 2D (or higher order)
arrays. Additionally, if this is a component, that is at top level of
the hierarchy and therefore dout will be connected to a pin it is also
not so good, to use an array type. -> Think about breaking it down to a
1D-array with the length of width*nbits.

Ralf

 

[killerhertz]

You have to define a type, that will be used for dout.

I'm not sure I understand. Why do I have to define a type for dout?

At the moment, you try to define a type AND use it at the same time. The type should be defined in a package.

Where am I defining a type for dout? I'm using a standard array of type
std_logic_vector for the output port declaration... Besides, if I put a
type in my local package, the top level won't be able to see what the
type definition is, right?

I'm not too worried about synthesis and it's hard to see how things are
working when dealing with an enormous vector, i.e. my length*width =
1KB.

 

[Ralf Hildebrandt]

I'm not sure I understand. Why do I have to define a type for dout?
Where am I defining a type for dout? I'm using a standard array of type
std_logic_vector for the output port declaration...

"a standard array of type std_logic_vector" ist not a type. This is a thing, that declares
a type.

Besides, if I put a
type in my local package, the top level won't be able to see what the
type definition is, right?

No - the definition is visible, because the package is included with the

library my_lib;
use my_lib.my_package.all;

before the entity.

I'm not too worried about synthesis and it's hard to see how things are
working when dealing with an enormous vector, i.e. my length*width =
1KB.

The problem is not the length of the vector, but if your signal is one- or two-dimensional
(if you have an older synthesis tool).


Ralf

 

[Brandon]

I understand that the package includes the type, but since I am using a
generic, how is the package going to know how to constrain the
std_logic_vector?

I guess the problem is that you can't have an array of
std_logic_vectors. I tried to compile:
<SNIP>
library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------------------------------------
-- PACKAGE
-------------------------------------------------------------------------------
package srsipo_g_pkg is

-----------------------------------------------------------------------------
-- constants
----------------------------------------------------------------
-- types
--------------------------------------------------------------------
-- type ARRAYSTDLV_T is array(natural range <>) of
std_logic_vector(natural range <>);
type ARRAY2DOFBIT_T is array(natural range <>, natural range <>) of
bit;

end srsipo_g_pkg;
</SNIP>

But I get a compile error on the first type (commented out now). I did
some searching and it seems I can't do that. Some usenet threads on
this area suggested using an unconstrained array of type bit, as I have
written above, which compiled and simulated correctly.

I can't remember the reason, but I was always told by profs to avoid
use of bit and bit_vector for synthesis, and not to mix my designs with
std_logic_vector and bit_vector. Is this true?

I have both Ashenden's Designer's Guide and Cohen's book, but neither
seem to mention how to create generics with 2d ports in this manner, so
I'm a bit frustrated... I want to write realy solid, reusable VHDL
here. How is this issue addressed in practice? Bit arrays seem like a
'hack'?

Thanks.

 

[Ralf Hildebrandt]

I understand that the package includes the type, but since I am using a
generic, how is the package going to know how to constrain the
std_logic_vector?

The package has to define the array in an unconstrained way and in your entity the
constraints will be set.

-- type ARRAYSTDLV_T is array(natural range <>) of
std_logic_vector(natural range <>);

But I get a compile error on the first type (commented out now). I did
some searching and it seems I can't do that.

I'm not shure if it is possible and don't have a VHDL compiler at hand, but what about

type ARRAYSTDLV_T is array(natural range <>) of std_logic_vector;

AFAIK this will result in in unconstrained array of an uncontrained std_logic_vector.

Some usenet threads on
this area suggested using an unconstrained array of type bit, as I have
written above, which compiled and simulated correctly.

I can't remember the reason, but I was always told by profs to avoid
use of bit and bit_vector for synthesis, and not to mix my designs with
std_logic_vector and bit_vector. Is this true?

Yes, I have read such thing too and I guess it is because bit does not have something like
'X' and therefore simulation may be different than synthesis.

I have both Ashenden's Designer's Guide and Cohen's book, but neither
seem to mention how to create generics with 2d ports in this manner

This is because it is rare to have an array in an entity, as usually this will result in
many wires and this leads to huge designs.

I want to write realy solid, reusable VHDL
here. How is this issue addressed in practice? Bit arrays seem like a
'hack'?

Again I will suggest to use a 1D array of size width*nbits. ;-)

Ralf