undeclared loop variable

[Brad Smallridge]

It seems that I can drop this into a testbench without
declaring col as a signal or a variable or anything.
What is vhdl doing with col?

for col in 1 to 16 loop
wait for clkperiod;
end loop;

 

[Kai Harrekilde-Petersen]

It seems that I can drop this into a testbench without
declaring col as a signal or a variable or anything.
What is vhdl doing with col?

VHDL considers the iteration variable to be constant for each pass
through the loop.

Regards,


Kai

 

[My Name]

It seems that I can drop this into a testbench without
declaring col as a signal or a variable or anything.
What is vhdl doing with col?

for col in 1 to 16 loop
wait for clkperiod;
end loop;

the only potential draw back that I see to this type of a construct is
that you can't reference "col" anywhere outside of the loop

 

[Neo]

The looping index is considered an implicit variable in vhdl and is
local to the for loop.

 

[Alan Fitch]

The looping index is considered an implicit variable in vhdl and is
local to the for loop.

In fact as Kai pointed out, the loop index is a constant.

All that means in practice is that you can't, for instance, do

col := 10;

inside the loop.

regards
Alan

 

[Paul Uiterlinden]

the only potential draw back that I see to this type of a construct is
that you can't reference "col" anywhere outside of the loop

I don't see that as a drawback. What value would you expect "col" to
have outside the loop anyway?

Paul.

 

[Jonathan Bromley]

[VHDL 'for' loop index is an implied constant within the loop...]

the only potential draw back that I see to this type of a construct is
that you can't reference "col" anywhere outside of the loop

Can you show me an example of this kind of thing that I could
read and yet still retain my lunch?
--
Jonathan Bromley, Consultant

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[Michael]

I don't see that as a drawback. What value would you expect "col" to
have outside the loop anyway?

Paul.

well, neither do I really.