undeclared loop variable

Discussion in 'VHDL' started by Brad Smallridge, Mar 23, 2005.

  1. It seems that I can drop this into a testbench without
    declaring col as a signal or a variable or anything.
    What is vhdl doing with col?

    for col in 1 to 16 loop
    wait for clkperiod;
    end loop;
    Brad Smallridge, Mar 23, 2005
    #1
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  2. "Brad Smallridge" <> writes:

    > It seems that I can drop this into a testbench without
    > declaring col as a signal or a variable or anything.
    > What is vhdl doing with col?


    VHDL considers the iteration variable to be constant for each pass
    through the loop.

    Regards,


    Kai
    --
    Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
    Kai Harrekilde-Petersen, Mar 23, 2005
    #2
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  3. Brad Smallridge

    My Name Guest

    Brad Smallridge wrote:

    > It seems that I can drop this into a testbench without
    > declaring col as a signal or a variable or anything.
    > What is vhdl doing with col?
    >
    > for col in 1 to 16 loop
    > wait for clkperiod;
    > end loop;
    >
    >



    the only potential draw back that I see to this type of a construct is
    that you can't reference "col" anywhere outside of the loop
    My Name, Mar 24, 2005
    #3
  4. Brad Smallridge

    Neo Guest

    The looping index is considered an implicit variable in vhdl and is
    local to the for loop.
    Neo, Mar 24, 2005
    #4
  5. Brad Smallridge

    Alan Fitch Guest

    Neo wrote:
    > The looping index is considered an implicit variable in vhdl and is
    > local to the for loop.
    >


    In fact as Kai pointed out, the loop index is a constant.

    All that means in practice is that you can't, for instance, do

    col := 10;

    inside the loop.

    regards
    Alan

    --

    Alan Fitch
    Doulos Ltd
    http://www.doulos.com
    Alan Fitch, Mar 24, 2005
    #5
  6. My Name wrote:
    >
    >> for col in 1 to 16 loop
    >> wait for clkperiod;
    >> end loop;

    >
    > the only potential draw back that I see to this type of a construct is
    > that you can't reference "col" anywhere outside of the loop


    I don't see that as a drawback. What value would you expect "col" to
    have outside the loop anyway?

    Paul.
    Paul Uiterlinden, Mar 24, 2005
    #6
  7. On Thu, 24 Mar 2005 00:30:14 -0700, My Name <> wrote:

    [VHDL 'for' loop index is an implied constant within the loop...]
    >the only potential draw back that I see to this type of a construct is
    >that you can't reference "col" anywhere outside of the loop


    Can you show me an example of this kind of thing that I could
    read and yet still retain my lunch?
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
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    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
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    Jonathan Bromley, Mar 24, 2005
    #7
  8. Brad Smallridge

    Michael Guest

    Paul Uiterlinden wrote:
    > My Name wrote:
    >
    >>
    >>> for col in 1 to 16 loop
    >>> wait for clkperiod;
    >>> end loop;

    >>
    >>
    >> the only potential draw back that I see to this type of a construct is
    >> that you can't reference "col" anywhere outside of the loop

    >
    >
    > I don't see that as a drawback. What value would you expect "col" to
    > have outside the loop anyway?
    >
    > Paul.



    well, neither do I really.
    Michael, Mar 25, 2005
    #8
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