unexplainable Problem on Spartan 3

Discussion in 'VHDL' started by thomas.neitzel@gmail.com, Dec 18, 2006.

  1. Guest

    Greetings to all !

    I started programming with VHDL two months ago. Now I want to implement
    a project on a Spartan 3 (XC3S50 VQ100). The software I´m using is the
    ISE Webpack 8.2.03i (Application Version: I.34).
    This project is later supposed to be a bit error testing instance in
    combination with an Microcontroller that is used to read out an compare
    the sended and received data from the block RAMs of the Spartan 3.
    I tested the components I used as standalone-designs and they all seem
    to function but when I try to make one pice of all designs the FPGA
    doesn´t show any expected behaviour at all-even some simple LED I
    integrated in the design to indicate if the clock is active don't start
    flashing.

    Although i know it's probably not the smartest way to ask for help but
    as I need this project to function for my thesis i have no other ideas
    than posting the whole code - any words are very appreciated (the
    comments are in german and not so important)!!!

    p.s.: It would also help if someone would just copy and paste this code
    into a new projektfile to find out if it´s running(simplest
    indication: the State LED_Z0 should be on and the LED_Z1 should be
    flashing) on his hardware.

    #UCF - File :
    ****************************************************************************************************

    NET "CLK_IN" LOC = "P36" | IOSTANDARD = LVTTL ; #Takt vom
    Meltemi-Board (66 MHz)

    NET "CLK_fromMC" LOC = "P39" | IOSTANDARD = LVTTL ;#Takt com MC
    NET "DATA_toMC<0>" LOC = "P30" | IOSTANDARD = LVTTL
    ;#Datenleitungen
    NET "DATA_toMC<1>" LOC = "P32" | IOSTANDARD = LVTTL ;
    NET "DATA_toMC<2>" LOC = "P34" | IOSTANDARD = LVTTL ;
    NET "DATA_toMC<3>" LOC = "P35" | IOSTANDARD = LVTTL ;
    NET "MC_READY" LOC = "P43" | IOSTANDARD = LVTTL ;#MC ist fertig mit
    Auslesen
    NET "MC_READ" LOC = "P44" | IOSTANDARD = LVTTL ;#MC soll mit Auslesen
    beginnen

    NET "INDICATION_MUXtoMC<1>" LOC = "P47" | IOSTANDARD = LVTTL ;
    NET "INDICATION_MUXtoMC<0>" LOC = "P59" | IOSTANDARD = LVTTL ;

    NET "LED_Z0" LOC = "P72" | IOSTANDARD = LVTTL ;
    NET "LED_Z1" LOC = "P50" | IOSTANDARD = LVTTL ;
    NET "LED_Z2" LOC = "P55" | IOSTANDARD = LVTTL ;
    ###############LVDS-Kanäle###############################
    NET "LVDS_Nr" LOC = "P88" | IOSTANDARD = LVDSEXT_25 ;#r: receive
    NET "LVDS_Ns" LOC = "P90" | IOSTANDARD = LVDSEXT_25 ;#s: send
    NET "LVDS_Pr" LOC = "P87" | IOSTANDARD = LVDSEXT_25 ;
    NET "LVDS_Ps" LOC = "P89" | IOSTANDARD = LVDSEXT_25 ;

    ################TASTER####################################
    NET "BUTTON" LOC = "P21" | IOSTANDARD = LVTTL ;#USERSTART

    --Topmodule -File:
    **********************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity TOPMODULE is
    generic(
    WAIT_WIDTH_USERSTART : positive := 28;
    WAIT_WIDTH_MC_READY : positive := 10;
    CNT_WIDTH : positive := 25
    );
    Port ( CLK_IN : in STD_LOGIC;
    MC_READY : in STD_LOGIC;
    BUTTON : in std_logic;
    LVDS_Pr : in STD_LOGIC; --receive
    LVDS_Nr : in STD_LOGIC;
    LVDS_Ps : out STD_LOGIC;--send
    LVDS_Ns : out STD_LOGIC;
    LED_Z0 : out STD_LOGIC;
    LED_Z1 : out STD_LOGIC;
    LED_Z2 : out STD_LOGIC;
    DATA_toMC : out STD_LOGIC_VECTOR (3 downto 0);
    MC_READ : out STD_LOGIC;
    CLK_fromMC : in std_logic;
    INDICATION_MUXtoMC : out std_logic_vector(1 downto 0)
    );
    end TOPMODULE;

    architecture Behavioral of TOPMODULE is

    component STATE_MACHINE
    port(CLKX1 : in std_logic;
    USER_START : in std_logic;
    ADDRESS_CONTROL_FINISH : in std_logic;
    MC_READY : in std_logic;
    BRAM1_EN_toMUX : out std_logic; --Ausgangssignale zu BRAM1
    BRAM1_EN_SEND : out std_logic;
    BRAM1_RESET_toMUX : out std_logic;
    BRAM1_RESET_SEND : out std_logic;
    BRAM2_EN_RECEIVE : out std_logic; --Ausgangssignale zu BRAM2
    BRAM2_EN_toMUX : out std_logic;
    BRAM2_RESET_toMUX : out std_logic;
    BRAM2_WRITE_EN : out std_logic;
    MUX_RESET : out std_logic;
    DES_EN : out std_logic;
    SER_NEN : out std_logic;
    SER_RESET : out std_logic;
    ADDR_CONTROL_RESET_NEN : out
    std_logic;--ADDRESS_CONTROL_RESET_(and)NotENable
    MC_READ : out std_logic;
    LED_Z0 : out std_logic; --die LEDs signalisieren den aktuellen
    Zustand
    LED_Z2 : out std_logic--;
    );
    end component;

    component ADDRESS_CONTROL
    generic(
    ADDRESS_WIDTH : positive := 10
    );
    Port ( CLKX1 : in std_logic;
    RESET_NEN : in STD_LOGIC;
    ADDR_BRAM1 : out STD_LOGIC_VECTOR (9 downto 0);
    ADDR_BRAM2 : out STD_LOGIC_VECTOR (9 downto 0);
    FINISH : out std_logic
    );
    end component;

    component SER16to1
    Port ( CLKX8 : in std_logic; --8facher Takt (bezogen auf den Takt des
    16 Bit breiten Datenbus)
    CLKX8_180 : in std_logic; --8facher Takt invertiert
    RESET : in std_logic; --Reseteingang
    NotENABLE : in std_logic;
    DATA_PARALLEL : in std_logic_vector(15 downto 0);
    ODATA_LVDSP : out std_logic;
    ODATA_LVDSN : out std_logic);
    end component;

    component DES1to16
    Port ( ENABLE : in std_logic; --mit DCM_LOCKED verbinden
    IDATA_LVDSP : in std_logic;
    IDATA_LVDSN : in std_logic;
    CLKX8 : in STD_LOGIC;
    CLKX8_180 : in STD_LOGIC;
    CLKX1 : in STD_LOGIC;
    DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0)
    );
    end component;

    component MUX
    generic(
    DATA_WIDTH: positive := 4;--Breite des Datenbusses
    ADRESS_WIDTH_toMC: positive := 12;
    CONTROL_WIDTH: positive := 2--Anzahl der Steuerleitungen
    );
    Port ( DATA1 : in STD_LOGIC_VECTOR (3 downto 0);--Daten von BRAM1
    DATA2 : in STD_LOGIC_VECTOR (3 downto 0);--Daten von BRAM2
    DATA_OUT : out STD_LOGIC_VECTOR (3 downto 0);--Datenbus zum
    Mikrocontroller
    ADRESS1 : out std_logic_vector(11 downto 0);--Adressbusse zu den
    BRAMs
    ADRESS2 : out std_logic_vector(11 downto 0);
    RESET : in std_logic;--asynchrones Resetsignal von der
    State-Machine
    INDICATION : out STD_LOGIC_VECTOR(1 downto 0);--Kontrollbus
    zum Mikrocontroller
    CLK_extMC : in STD_LOGIC;--Auslesetakt für die BRAMs (vom
    Mikrocontroller generiert)
    CLK_fromMC :eek:ut STD_LOGIC
    );
    end component;

    component BRAM_SEND
    port(
    DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
    Data Output
    DATA_toSER : out std_logic_vector(15 downto 0); -- Port B
    16-bit Data Output
    ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
    Address Input
    ADDRESS_SEND: in std_logic_vector(9 downto 0); -- Port B 10-bit
    Address Input
    CLK_MUX : in std_logic; -- Port A Clock
    CLKX1 : in std_logic; -- Port B Clock
    EN_toMUX : in std_logic; -- Port A RAM Enable Input
    EN_SEND : in std_logic; -- PortB RAM Enable Input
    RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
    Input
    RESET_SEND : in std_logic -- Port B Synchronous Set/Reset Input
    );
    end component;

    component BRAM_RECEIVE
    port(
    DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
    Data Output
    DATA_fromDES : in std_logic_vector(15 downto 0); -- Port B
    16-bit Data Intput
    ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
    Address Input
    ADDRESS_RECEIVE: in std_logic_vector(9 downto 0); -- Port B
    10-bit Address Input
    CLK_MUX : in std_logic; -- Port A Clock
    CLKX1_PS : in std_logic; -- Port B Clock (PS: phase-shifted)
    Verzögerung des DUTs
    EN_toMUX : in std_logic; -- Port A RAM Enable Input
    EN_RECEIVE : in std_logic; -- PortB RAM Enable Input
    RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
    Input
    WRITE_ENABLE : in std_logic
    );
    end component;


    component GENERATE_CLOCK
    Port ( CLKIN_IN : in std_logic; --Oszillator mit 66 MHz
    (meltemi: P36)
    CLKDV_OUT : out std_logic; --33 Mhz Takt
    CLKFX_OUT : out std_logic; --264 MHz Takt
    CLKFX180_OUT : out std_logic
    );
    end component;


    signal CLKX1, CLKX8, CLKX8_180 : std_logic;
    signal ADDRESS_CONTROL_FINISH, BRAM1_EN_SEND, BRAM1_RESET_toMUX,
    BRAM1_RESET_SEND : std_logic;
    signal BRAM2_EN_RECEIVE, BRAM2_RESET_toMUX, BRAM2_WRITE_EN, MUX_RESET :
    std_logic;
    signal DES_EN, SER_NEN, SER_RESET, ADDR_CONTROL_RESET_NEN : std_logic;
    signal ADDR_BRAM1, ADDR_BRAM2 : std_logic_vector(9 downto 0);
    signal DATA_toSER16to1, DATA_fromDES1to16 : std_logic_vector(15 downto
    0);
    signal DATA_toMUX_BRAM_S, DATA_toMUX_BRAM_R : std_logic_vector(3 downto
    0);
    signal ADDRESS_BRAM_SEND, ADDRESS_BRAM_RECEIVE : std_logic_vector(11
    downto 0);
    signal BRAM1_EN_toMUX, BRAM2_EN_toMUX : std_logic;

    signal USERSTART : std_logic := '0';

    signal CLK_fromMC_buffered : STD_LOGIC;


    --Taster :
    --Tatser1 :
    signal SHIFT_PB1 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
    signal BUTTON_DEBOUNCED1 : std_logic := '0';
    signal LEVEL1 : std_logic := '0';


    --CLK-Indication :
    signal CNT : std_logic_vector(CNT_WIDTH-1 downto 0) := (others => '0');
    constant MAX_CNT : std_logic_vector(CNT_WIDTH-1 downto 0) := (others =>
    '1');
    signal LEVEL : std_logic := '0';


    begin

    inst_GC : GENERATE_CLOCK
    port map(
    CLKIN_IN => CLK_IN, --externer Takt
    CLKDV_OUT => CLKX1, --33 Mhz Takt
    CLKFX_OUT => CLKX8, --264 MHz Takt
    CLKFX180_OUT => CLKX8_180--CLKX8 um 180° phasenverschoben

    );

    inst_SM : STATE_MACHINE
    port map(
    CLKX1 => CLKX1,
    USER_START => USERSTART,
    ADDRESS_CONTROL_FINISH => ADDRESS_CONTROL_FINISH,
    MC_READY => MC_READY,--MC herausgenommen
    BRAM1_EN_toMUX => BRAM1_EN_toMUX, --Ausgangssignale zu BRAM1
    BRAM1_EN_SEND => BRAM1_EN_SEND,
    BRAM1_RESET_toMUX => BRAM1_RESET_toMUX,
    BRAM1_RESET_SEND => BRAM1_RESET_SEND,
    BRAM2_EN_RECEIVE => BRAM2_EN_RECEIVE, --Ausgangssignale zu BRAM2
    BRAM2_EN_toMUX => BRAM2_EN_toMUX,
    BRAM2_RESET_toMUX => BRAM2_RESET_toMUX,
    BRAM2_WRITE_EN => BRAM2_WRITE_EN,
    MUX_RESET => MUX_RESET,
    DES_EN => DES_EN,
    SER_NEN => SER_NEN,
    SER_RESET => SER_RESET,
    ADDR_CONTROL_RESET_NEN =>
    ADDR_CONTROL_RESET_NEN,--ADDRESS_CONTROL_RESET_(and)NotENable
    MC_READ => MC_READ,
    LED_Z0 => LED_Z0, --die LEDs signalisieren den aktuellen Zustand
    LED_Z2 => LED_Z2
    );

    inst_AC : ADDRESS_CONTROL
    port map(
    CLKX1 => CLKX1,
    RESET_NEN => ADDR_CONTROL_RESET_NEN,
    ADDR_BRAM1 => ADDR_BRAM1, --BRAM_SEND
    ADDR_BRAM2 => ADDR_BRAM2, --BRAM_RECEIVE
    FINISH => ADDRESS_CONTROL_FINISH
    );

    inst_SER : SER16to1
    port map(
    CLKX8 => CLKX8, --8facher Takt (bezogen auf den Takt des 16 Bit
    breiten Datenbus)
    CLKX8_180 => CLKX8_180, --8facher Takt invertiert
    RESET => SER_RESET, --Reseteingang
    NotENABLE => SER_NEN,
    DATA_PARALLEL => DATA_toSER16to1,
    ODATA_LVDSP => LVDS_Ps,
    ODATA_LVDSN => LVDS_Ns
    );

    inst_DES : DES1to16
    port map(
    ENABLE => DES_EN, --mit DCM_LOCKED verbinden
    IDATA_LVDSP => LVDS_Pr,
    IDATA_LVDSN => LVDS_Nr,
    CLKX8 => CLKX8,
    CLKX8_180 => CLKX8_180,
    CLKX1 => CLKX1,
    DATA_OUT => DATA_fromDES1to16
    );

    inst_MUX : MUX
    port map(
    DATA1 => DATA_toMUX_BRAM_S,--Daten von BRAM1
    DATA2 => DATA_toMUX_BRAM_R,--Daten von BRAM2
    DATA_OUT => DATA_toMC,--Datenbus zum Mikrocontroller
    ADRESS1 => ADDRESS_BRAM_SEND,--Adressbusse zu den BRAMs
    ADRESS2 => ADDRESS_BRAM_RECEIVE,
    RESET => MUX_RESET,--asynchrones Resetsignal von der State-Machine
    INDICATION => INDICATION_MUXtoMC,--Kontrollbus zum
    Mikrocontroller
    CLK_extMC => CLK_fromMC--Auslesetakt für die BRAMs (vom
    Mikrocontroller generiert)
    );

    inst_BRAM_S : BRAM_SEND --BRAM1
    port map(
    DATA_toMUX => DATA_toMUX_BRAM_S, -- Port A 4-bit Data Output
    DATA_toSER => DATA_toSER16to1, -- Port B 16-bit Data Output
    ADDRESS_MUX => ADDRESS_BRAM_SEND, -- Port A 12-bit Address Input
    ADDRESS_SEND => ADDR_BRAM1, -- Port B 10-bit Address Input
    CLK_MUX => CLK_fromMC_buffered, -- Port A Clock
    CLKX1 => CLKX1, -- Port B Clock
    EN_toMUX => BRAM1_EN_toMUX, -- Port A RAM Enable Input
    EN_SEND => BRAM1_EN_SEND, -- PortB RAM Enable Input
    RESET_toMUX => BRAM1_RESET_toMUX, -- Port A Synchronous
    Set/Reset Input
    RESET_SEND => BRAM1_RESET_SEND -- Port B Synchronous Set/Reset
    Input
    );

    inst_BRAM_R : BRAM_RECEIVE
    port map(
    DATA_toMUX => DATA_toMUX_BRAM_R, -- Port A 4-bit Data Output
    DATA_fromDES => DATA_fromDES1to16, -- Port B 16-bit Data
    Intput
    ADDRESS_MUX => ADDRESS_BRAM_RECEIVE, -- Port A 12-bit Address
    Input
    ADDRESS_RECEIVE => ADDR_BRAM2, -- Port B 10-bit Address Input
    CLK_MUX => CLK_fromMC_buffered, -- Port A Clock
    CLKX1_PS => CLKX1, -- Port B Clock (PS: phase-shifted)
    Verzögerung des DUTs
    EN_toMUX => BRAM2_EN_toMUX, -- Port A RAM Enable Input
    EN_RECEIVE => BRAM2_EN_RECEIVE, -- PortB RAM Enable Input
    RESET_toMUX => BRAM2_RESET_toMUX, -- Port A Synchronous
    Set/Reset Input
    WRITE_ENABLE => BRAM2_WRITE_EN
    );



    --CLK-Indication :
    CLK_indication: process(CLKX1)
    begin
    if (CLKX1'event and CLKX1 = '1') then
    if CNT = MAX_CNT then
    LEVEL <= not LEVEL;
    CNT <= (others => '0');
    else
    CNT <= CNT +1;
    end if;
    end if;
    end process;

    LED_Z1 <= LEVEL;
    --LED_Z1 <= '1';
    ----Taster1 :
    DEBOUNCE1: process(CLKX1)
    begin
    if (CLKX1'event and CLKX1 = '1') then
    -- Use a shIFt register to filter switch contact bounce
    SHIFT_PB1(2 downto 0) <= SHIFT_PB1(3 downto 1);
    SHIFT_PB1(3) <= BUTTON;
    if SHIFT_PB1(3 downto 0) = "0000" then
    BUTTON_DEBOUNCED1 <= '0';
    else
    BUTTON_DEBOUNCED1 <= '1';
    end if;
    end if;
    end process;

    SWITCH1: process(BUTTON_DEBOUNCED1)
    begin
    if (BUTTON_DEBOUNCED1'event and BUTTON_DEBOUNCED1 = '1') then
    LEVEL1 <= not LEVEL1;
    end if;
    end process;

    USERSTART <= LEVEL1;


    end Behavioral;

    --GENERATE_CLOCK-FILE :
    *********************************************************************************

    library ieee;
    use ieee.std_logic_1164.ALL;
    use ieee.numeric_std.ALL;
    library UNISIM;
    use UNISIM.Vcomponents.ALL;

    --konfiguriert für einen Eingangstakt der Frequenz 66 MHz

    entity GENERATE_CLOCK is
    port ( CLKIN_IN : in std_logic; --Oszillator mit 66 MHz
    (meltemi: P36)
    CLKDV_OUT : out std_logic; --33 Mhz Takt
    CLKFX_OUT : out std_logic; --264 MHz Takt
    CLKFX180_OUT : out std_logic
    );-- = '1' -> DCM eingeschwungen
    end GENERATE_CLOCK;

    architecture BEHAVIORAL of GENERATE_CLOCK is

    component BUFG
    port ( I : in std_logic;
    O : out std_logic);
    end component;

    component IBUFG
    port ( I : in std_logic;
    O : out std_logic);
    end component;

    -- Period Jitter (unit interval) for block DCM_INST = 0.17 UI
    -- Period Jitter (Peak-to-Peak) for block DCM_INST = 0.63 ns
    component DCM
    generic( CLK_FEEDBACK : string := "1X";
    CLKDV_DIVIDE : real := 2.0;
    CLKFX_DIVIDE : integer := 1;
    CLKFX_MULTIPLY : integer := 4; ---sonst 4 !!!
    CLKIN_DIVIDE_BY_2 : boolean := FALSE;
    CLKIN_PERIOD : real := 10.0;
    CLKOUT_PHASE_SHIFT : string := "NONE";
    DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
    DFS_FREQUENCY_MODE : string := "LOW";
    DLL_FREQUENCY_MODE : string := "LOW";
    DUTY_CYCLE_CORRECTION : boolean := TRUE;
    FACTORY_JF : bit_vector := x"8080";
    PHASE_SHIFT : integer := 0;
    STARTUP_WAIT : boolean := FALSE;
    DSS_MODE : string := "NONE");
    port ( CLKIN : in std_logic;
    CLKFB : in std_logic;
    RST : in std_logic;
    PSEN : in std_logic;
    PSINCDEC : in std_logic;
    PSCLK : in std_logic;
    DSSEN : in std_logic;
    CLK0 : out std_logic;
    CLK90 : out std_logic;
    CLK180 : out std_logic;
    CLK270 : out std_logic;
    CLKDV : out std_logic;
    CLK2X : out std_logic;
    CLK2X180 : out std_logic;
    CLKFX : out std_logic;
    CLKFX180 : out std_logic;
    STATUS : out std_logic_vector (7 downto 0);
    LOCKED : out std_logic;
    PSDONE : out std_logic);
    end component;

    signal CLKDV_BUF : std_logic;
    signal CLKFB_IN : std_logic;
    signal CLKFX_BUF : std_logic;
    signal CLKFX180_BUF : std_logic;
    signal CLKIN_IBUFG : std_logic;
    signal CLK0_BUF : std_logic;
    signal GND1 : std_logic;

    begin
    GND1 <= '0';
    CLKDV_BUFG_INST : BUFG
    port map (I=>CLKDV_BUF,
    O=>CLKDV_OUT);

    CLKFX_BUFG_INST : BUFG
    port map (I=>CLKFX_BUF,
    O=>CLKFX_OUT);

    CLKFX180_BUFG_INST : BUFG
    port map (I=>CLKFX180_BUF,
    O=>CLKFX180_OUT);

    CLKIN_IBUFG_INST : IBUFG
    port map (I=>CLKIN_IN,
    O=>CLKIN_IBUFG);

    CLK0_BUFG_INST : BUFG
    port map (I=>CLK0_BUF,
    O=>CLKFB_IN);

    DCM_INST : DCM
    generic map( CLK_FEEDBACK => "1X",
    CLKDV_DIVIDE => 2.0,
    CLKFX_DIVIDE => 1,
    CLKFX_MULTIPLY => 4,
    CLKIN_DIVIDE_BY_2 => FALSE,
    CLKIN_PERIOD => 15.1515,
    CLKOUT_PHASE_SHIFT => "NONE",
    DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
    DFS_FREQUENCY_MODE => "HIGH",
    DLL_FREQUENCY_MODE => "LOW",
    DUTY_CYCLE_CORRECTION => TRUE,
    FACTORY_JF => x"8080",
    PHASE_SHIFT => 0,
    STARTUP_WAIT => TRUE)
    port map (CLKFB=>CLKFB_IN,
    CLKIN=>CLKIN_IBUFG,
    DSSEN=>GND1,
    PSCLK=>GND1,
    PSEN=>GND1,
    PSINCDEC=>GND1,
    RST=>'0',
    CLKDV=>CLKDV_BUF,
    CLKFX=>CLKFX_BUF,
    CLKFX180=>CLKFX180_BUF,
    CLK0=>CLK0_BUF,
    CLK2X=>open,
    CLK2X180=>open,
    CLK90=>open,
    CLK180=>open,
    CLK270=>open,
    LOCKED=>open,
    PSDONE=>open,
    STATUS=>open);


    end BEHAVIORAL;

    --STATE_MACHINE-FILE :
    ************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity STATE_MACHINE is
    port(CLKX1 : in std_logic;
    USER_START : in std_logic;
    ADDRESS_CONTROL_FINISH : in std_logic;
    MC_READY : in std_logic;
    BRAM1_EN_toMUX : out std_logic; --Ausgangssignale zu BRAM1
    BRAM1_EN_SEND : out std_logic;
    BRAM1_RESET_toMUX : out std_logic;
    BRAM1_RESET_SEND : out std_logic;
    BRAM2_EN_RECEIVE : out std_logic; --Ausgangssignale zu BRAM2
    BRAM2_EN_toMUX : out std_logic;
    BRAM2_RESET_toMUX : out std_logic;
    BRAM2_WRITE_EN : out std_logic;
    MUX_RESET : out std_logic;
    DES_EN : out std_logic;
    SER_NEN : out std_logic;
    SER_RESET : out std_logic;
    ADDR_CONTROL_RESET_NEN : out
    std_logic;--ADDRESS_CONTROL_RESET_(and)NotENable
    MC_READ : out std_logic;
    LED_Z0 : out std_logic;
    LED_Z2 : out std_logic--;
    );
    end STATE_MACHINE;--Moore-Automat

    architecture Behavioral of STATE_MACHINE is

    type STATES is (Z0, Z1, Z2);
    signal STATE: STATES := Z0;
    signal NEXT_S: STATES := Z0;


    signal STATE_Z0, STATE_Z2 : std_logic;


    begin

    STATE_MEMORY: process(CLKX1)
    begin
    if CLKX1'event and CLKX1 = '1' then--eventuell Flanke ändern?
    STATE <= NEXT_S;
    end if;
    end process;

    DEFINE_NEXT_STATE: process(USER_START, ADDRESS_CONTROL_FINISH, MC_READY
    ,STATE)
    begin
    case STATE is
    when Z0 => if USER_START = '1' then
    NEXT_S <= Z1;
    else
    NEXT_S <=Z0;
    end if;
    when Z1 => if ADDRESS_CONTROL_FINISH = '1' then
    NEXT_S <= Z2;
    else
    NEXT_S <=Z1;
    end if;
    when Z2 => if MC_READY = '1' then
    NEXT_S <= Z0;
    else
    NEXT_S <=Z2;
    end if;
    end case;
    end process;

    SET_OUTPUTS: process(STATE)
    begin
    case STATE is
    when Z0 => BRAM1_EN_toMUX <= '0';
    BRAM1_EN_SEND <= '0';
    BRAM1_RESET_toMUX <= '1';
    BRAM1_RESET_SEND <= '1';
    BRAM2_EN_RECEIVE <= '0';
    BRAM2_EN_toMUX <= '0';
    BRAM2_RESET_toMUX <= '1';
    BRAM2_WRITE_EN <= '0';
    MUX_RESET <= '1';
    DES_EN <= '0';
    SER_NEN <= '1';
    SER_RESET <= '1';
    ADDR_CONTROL_RESET_NEN <= '1';
    MC_READ <= '0';
    when Z1 => BRAM1_EN_toMUX <= '0';
    BRAM1_EN_SEND <= '1';
    BRAM1_RESET_toMUX <= '1';
    BRAM1_RESET_SEND <= '0';
    BRAM2_EN_RECEIVE <= '1';
    BRAM2_EN_toMUX <= '0';
    BRAM2_RESET_toMUX <= '1';
    BRAM2_WRITE_EN <= '1';
    MUX_RESET <= '1';
    DES_EN <= '1';
    SER_NEN <= '0';
    SER_RESET <= '0';
    ADDR_CONTROL_RESET_NEN <= '0';
    MC_READ <= '0';
    when Z2 => BRAM1_EN_toMUX <= '1';
    BRAM1_EN_SEND <= '0';
    BRAM1_RESET_toMUX <= '0';
    BRAM1_RESET_SEND <= '1';--eventuall ändern !
    BRAM2_EN_RECEIVE <= '0';
    BRAM2_EN_toMUX <= '1';
    BRAM2_RESET_toMUX <= '0';
    BRAM2_WRITE_EN <= '0';
    MUX_RESET <= '0';
    DES_EN <= '0';
    SER_NEN <= '1';
    SER_RESET <= '1';
    ADDR_CONTROL_RESET_NEN <= '1';
    MC_READ <= '1';
    end case;
    end process;

    INDICATE_STATE: process(STATE)
    begin
    case STATE is
    when Z0 => STATE_Z0 <= '1';
    STATE_Z2 <= '0';
    when Z1 => STATE_Z0 <= '0';
    STATE_Z2 <= '0';
    when Z2 => STATE_Z0 <= '0';
    STATE_Z2 <= '1';
    end case;
    end process;


    LED_Z0 <= STATE_Z0; --die LEDs signalisieren den aktuellen Zustand
    LED_Z2 <= STATE_Z2;

    end Behavioral;

    ADDRESS_CONTROL-FILE :
    ********************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;


    entity ADDRESS_CONTROL is
    generic(
    ADDRESS_WIDTH : positive := 10
    );
    Port ( CLKX1 : in std_logic;
    RESET_NEN : in STD_LOGIC;
    ADDR_BRAM1 : out STD_LOGIC_VECTOR (ADDRESS_WIDTH-1 downto
    0);
    ADDR_BRAM2 : out STD_LOGIC_VECTOR (ADDRESS_WIDTH-1 downto
    0);
    FINISH : out std_logic
    );
    end ADDRESS_CONTROL;

    architecture Behavioral of ADDRESS_CONTROL is

    signal FINISH_FLAG : std_logic;
    signal CNT : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    constant MAX_ADDRESS : std_logic_vector(ADDRESS_WIDTH-1 downto 0) :=
    "1111111111";

    begin

    CHANGE_ADDRESS: process(CLKX1)
    begin
    if CLKX1'event and CLKX1 = '1' then
    if RESET_NEN = '1' then
    CNT <= (others => '0');
    FINISH_FLAG <= '0';
    else
    if CNT = MAX_ADDRESS then
    FINISH_FLAG <= '1';
    else
    CNT <= CNT + 1;
    FINISH_FLAG <= '0';
    end if;
    end if;
    end if;
    end process;

    ADDR_BRAM1 <= CNT;
    ADDR_BRAM2 <= CNT;

    FINISH <= FINISH_FLAG;

    end Behavioral;

    --SER-FILE :
    ****************************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity SER16to1 is
    Port ( CLKX8 : in std_logic; --8facher Takt (bezogen auf den Takt des
    16 Bit breiten Datenbus)
    CLKX8_180 : in std_logic; --8facher Takt invertiert
    RESET : in std_logic; --Reseteingang
    NotENABLE : in std_logic;
    DATA_PARALLEL : in std_logic_vector(15 downto 0);
    ODATA_LVDSP : out std_logic;
    ODATA_LVDSN : out std_logic);
    end SER16to1;

    architecture Behavioral of SER16to1 is

    signal DATA_POS_EDGE, DATA_NEG_EDGE, DOUBLE_R_DATA : std_logic;
    signal CNT, CNT0: std_logic_vector(2 downto 0):= (others => '0');

    begin

    OFDDRRSE_inst : FDDRRSE --double datarate
    port map (
    Q => DOUBLE_R_DATA, -- Data output (connect directly to
    top-level port)
    C0 => CLKX8, -- 0 degree clock input
    C1 => CLKX8_180, -- 180 degree clock input
    --Commonly, the Digital Clock Manager
    --(DCM) generates the two clock signals by mirroring an
    --incoming signal, then shifting it 180 degrees. This approach
    --ensures minimal skew between the two signals.
    CE => '1', -- Clock enable input
    D0 => DATA_POS_EDGE, -- Posedge data input
    D1 => DATA_NEG_EDGE, -- Negedge data input
    R => NotENABLE, -- Synchronous reset input
    S => '0' -- Synchronous preset input
    );

    OBUFDS_inst : OBUFDS --LVDS-Output
    generic map(
    IOSTANDARD => "LVDSEXT_25")--Standard: siehe Datasheet S.62(Tabelle
    36)
    port map (
    O => ODATA_LVDSP, -- Diff_p output (connect directly to
    top-level port)
    OB => ODATA_LVDSN, -- Diff_n output (connect directly to
    top-level port)
    I => DOUBLE_R_DATA -- Buffer input
    );

    --***********************************************************************
    -- Prozess: COUNT
    --
    --Der Prozess fungiert als taktsynchroner Zähler von 0 bis 7 mit
    --synchronem Reseteingang(highaktiv), der den Zählerstand auf Null
    setzt.
    --
    -- Input (->): CLK8X, RESET
    --***********************************************************************
    COUNT: process(CLKX8_180)
    begin
    if(CLKX8_180'event and CLKX8_180='1') then
    if RESET = '1' then
    CNT <= (others => '0');
    CNT0 <= (others => '0');
    else
    CNT <= CNT + '1';
    CNT0 <= CNT;
    end if;
    end if;
    end process;


    --***********************************************************************
    -- Prozess: MULTIPLEX
    --
    --Der Prozess legt in Abhängigkeit des Zählerstandes in CNT zwei
    --aufeinanderfolgende Bits des parallelen Datenbusses DATA_PARALLEL an
    --DATA_POS_EDGE und DATA_NEG_EDGE an.
    --
    -- Input (->): CLK8X_180, DATA_PARALLEL, CNT
    -- Output(<-): DATA_POS_EDGE, DATA_NEG_EDGE
    --***********************************************************************
    MULTIPLEX: process(CLKX8_180)
    begin
    if(CLKX8_180'event and CLKX8_180='1') then
    if(CNT0 = 0) then
    DATA_POS_EDGE <= DATA_PARALLEL(0);--eventuell Reihenfolge aus
    SERDES-File verwenden
    DATA_NEG_EDGE <= DATA_PARALLEL(1);
    elsif(CNT0 = 1) then
    DATA_POS_EDGE <= DATA_PARALLEL(2);
    DATA_NEG_EDGE <= DATA_PARALLEL(3);
    elsif(CNT0 = 2) then
    DATA_POS_EDGE <= DATA_PARALLEL(4);
    DATA_NEG_EDGE <= DATA_PARALLEL(5);
    elsif(CNT0 = 3) then
    DATA_POS_EDGE <= DATA_PARALLEL(6);
    DATA_NEG_EDGE <= DATA_PARALLEL(7);
    elsif(CNT0 = 4) then
    DATA_POS_EDGE <= DATA_PARALLEL(8);
    DATA_NEG_EDGE <= DATA_PARALLEL(9);
    elsif(CNT0 = 5) then
    DATA_POS_EDGE <= DATA_PARALLEL(10);
    DATA_NEG_EDGE <= DATA_PARALLEL(11);
    elsif(CNT0 = 6) then
    DATA_POS_EDGE <= DATA_PARALLEL(12);
    DATA_NEG_EDGE <= DATA_PARALLEL(13);
    else
    DATA_POS_EDGE <= DATA_PARALLEL(14);
    DATA_NEG_EDGE <= DATA_PARALLEL(15);
    end if;
    end if;
    end process;--nach dem Reset wird die seriellen Daten mit CLK8X/2
    verzögert ausgegeben


    end Behavioral;


    --DES-FILE :
    ****************************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    -- Die Daten werden nach 2 Perioden von CLKX1 an DATA_OUT ausgegeben
    library UNISIM;
    use UNISIM.VComponents.all;

    entity DES1to16 is
    Port ( ENABLE : in std_logic; --mit DCM_LOCKED verbinden
    IDATA_LVDSP : in std_logic;
    IDATA_LVDSN : in std_logic;
    CLKX8 : in STD_LOGIC;
    CLKX8_180 : in STD_LOGIC;
    CLKX1 : in STD_LOGIC;
    DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0));
    end DES1to16;

    architecture Behavioral of DES1to16 is

    signal DOUBLE_RATE_DATA_DES, DATA_NEG_EDGE, DATA_POS_EDGE : std_logic;
    signal DD2 : std_logic_vector(15 downto 0);
    signal DD1 : std_logic_vector(13 downto 0);

    begin

    IBUFDS_inst : IBUFDS
    generic map (
    IOSTANDARD => "LVDSEXT_25")
    port map (
    O => DOUBLE_RATE_DATA_DES, -- Clock buffer output
    I => IDATA_LVDSP, -- Diff_p clock buffer input (connect directly
    to top-level port)
    IB => IDATA_LVDSN -- Diff_n clock buffer input (connect directly
    to top-level port)
    );

    double_data_rate1: process(CLKX8)
    begin
    if CLKX8'event and CLKX8 = '1' then
    DATA_POS_EDGE <= DOUBLE_RATE_DATA_DES;
    end if;
    end process;

    double_data_rate2: process(CLKX8_180)
    begin
    if CLKX8_180'event and CLKX8_180 = '1' then
    DATA_NEG_EDGE <= DOUBLE_RATE_DATA_DES;
    end if;
    end process;

    process(CLKX8_180) begin
    if(CLKX8_180'event and CLKX8_180='1') then
    DD2(15) <= DATA_POS_EDGE;
    DD2(14) <= DATA_NEG_EDGE;
    DD2(13) <= DD2(15);
    DD2(12) <= DD2(14);
    DD2(11) <= DD2(13);
    DD2(10) <= DD2(12);
    DD2(9) <= DD2(11);
    DD2(8) <= DD2(10);
    DD2(7) <= DD2(9);
    DD2(6) <= DD2(8);
    DD2(5) <= DD2(7);
    DD2(4) <= DD2(6);
    DD2(3) <= DD2(5);
    DD2(2) <= DD2(4);
    DD2(1) <= DD2(3);
    DD2(0) <= DD2(2);
    end if;
    end process;

    process(CLKX1) begin
    if(CLKX1'event and CLKX1 = '1') then
    DD1 <= DD2(15 downto 2);
    end if;
    end process;

    process(CLKX1) begin
    if(CLKX1'event and CLKX1 = '1') then
    if ENABLE = '1' then
    DATA_OUT <= DD2(1 downto 0) & DD1;
    else
    DATA_OUT <= (others => '0');
    end if;
    end if;
    end process;


    end Behavioral;


    --MUX-FILE :
    ****************************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity MUX is
    generic(
    DATA_WIDTH: positive := 4;--Breite des Datenbusses
    ADRESS_WIDTH_toMC: positive := 12;
    CONTROL_WIDTH: positive := 2--Anzahl der Steuerleitungen
    );
    Port ( DATA1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);--Daten
    von BRAM1
    DATA2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);--Daten
    von BRAM2
    DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto
    0);--Datenbus zum Mikrocontroller
    ADRESS1 : out std_logic_vector(ADRESS_WIDTH_toMC-1 downto
    0);--Adressbusse zu den BRAMs
    ADRESS2 : out std_logic_vector(ADRESS_WIDTH_toMC-1 downto 0);
    RESET : in std_logic;--asynchrones Resetsignal von der
    State-Machine
    INDICATION : out STD_LOGIC_VECTOR(CONTROL_WIDTH-1 downto
    0);--Kontrollbus zum Mikrocontroller
    CLK_extMC : in STD_LOGIC;--Auslesetakt für die BRAMs (vom
    Mikrocontroller generiert)
    CLK_fromMC :eek:ut STD_LOGIC
    );
    end MUX;

    architecture Behavioral of MUX is


    signal CHOOSE: std_logic := '0';
    signal ADRESS : std_logic_vector(ADRESS_WIDTH_toMC-1 downto 0);
    signal CLK_MC : std_logic;
    signal DATA_OUTs : std_logic_vector(DATA_WIDTH-1 downto 0);
    constant MAX_ADRESS : std_logic_vector(ADRESS_WIDTH_toMC-1 downto 0) :=
    "111111111111";--:= (others => '1');

    begin

    IBUFG_inst : IBUFG
    generic map (
    IOSTANDARD => "LVTTL")--Vmax = 3,3 V
    port map (
    O => CLK_MC, -- Clock buffer output
    I => CLK_extMC -- Clock buffer input (connect directly to
    top-level port)
    );


    COUNT: process(RESET,CLK_MC)
    begin
    if RESET = '1' then
    ADRESS <= (others => '0'); --eventuell auf 2 oder 3 setzen
    (Verzögerung des DES)
    INDICATION <= "00";
    CHOOSE <= '0';
    DATA_OUTs <= "0000";
    elsif CLK_MC'event and CLK_MC = '1' then
    if ADRESS = MAX_ADRESS and CHOOSE = '1' then
    INDICATION <= "11";

    elsif CHOOSE = '1' then
    INDICATION <= "10";
    ADRESS <= ADRESS + 1;
    DATA_OUTs <= DATA2;

    CHOOSE <= not CHOOSE;
    elsif CHOOSE = '0' then
    INDICATION <= "01";
    DATA_OUTs <= DATA1;

    CHOOSE <= not CHOOSE;
    end if;
    end if;
    end process;

    ADRESS1 <= ADRESS;
    ADRESS2 <= ADRESS;

    DATA_OUT <= DATA_OUTs;

    CLK_fromMC <= CLK_MC;


    end Behavioral;


    --BRAM_SEND-FILE :
    *****************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity BRAM_SEND is
    port(
    DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
    Data Output
    DATA_toSER : out std_logic_vector(15 downto 0); -- Port B
    16-bit Data Output
    ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
    Address Input
    ADDRESS_SEND: in std_logic_vector(9 downto 0); -- Port B 10-bit
    Address Input
    CLK_MUX : in std_logic; -- Port A Clock
    CLKX1 : in std_logic; -- Port B Clock
    EN_toMUX : in std_logic; -- Port A RAM Enable Input
    EN_SEND : in std_logic; -- PortB RAM Enable Input
    RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
    Input
    RESET_SEND : in std_logic -- Port B Synchronous Set/Reset Input
    );
    end BRAM_SEND;

    architecture Behavioral of BRAM_SEND is

    begin

    RAMB16_S4_S18_instBRAM_S : RAMB16_S4_S18
    generic map (
    INIT_A => X"0", -- Value of output RAM registers on Port A at
    startup
    INIT_B => "000000000000000000", -- Value of output RAM registers
    on Port B at startup
    SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
    SRVAL_B => "000000000000000000", -- Port B ouput value upon SSR
    assertion
    WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
    NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
    NO_CHANGE
    SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING",
    "GENERATE_X_ONLY", "ALL
    -- The following INIT_xx declarations specify the initial
    contents of the RAM
    -- Port A Address 0 to 1023, Port B Address 0 to 255
    INIT_00 =>
    X"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa",
    INIT_01 =>
    X"31A24DB059A566389894651BBD99BD2D8C9B354390CB86B5E70923CC10B65204",
    INIT_02 =>
    X"B75A641ACB7C72335E48B321BA380BC5AE9283A6251BEA66393419843808728D",
    INIT_03 =>
    X"3D2602D4EB565E4BD3ED9E420A33DC4880330B8BE847CCD78EA28B0D1629203B",
    INIT_04 =>
    X"7B584C96B3261E267E525534B3690D7A2AD1CC72E9BEB9DC5AE412A0D3E34174",
    INIT_05 =>
    X"4764D5C1BA875991B1B88A0DC825861D6714624105DBEEC93E9559134288753B",
    INIT_06 =>
    X"2A24E99ECED52732D58D25C5872420D4D2B6DC080B272BEA253E5AA815B2AA5E",
    INIT_07 =>
    X"A9EAB4871BD31ED9E7ACA6A2A562D3997107CE0748D5273B21A54A715116623A",
    INIT_08 =>
    X"0E8D512E0DDDA220348A7EC887150339A019A1CADA6B6C67C646B272C65B3945",
    INIT_09 =>
    X"47658CE4977E28C8BA23A832911095B56EAD0D46DE2E6D6A23B0D6A022B798C8",
    INIT_0A =>
    X"6D5D528AC725EB0D5AC9AA396A985E2041340DCCE61726EA3E62AD8796790D74",
    INIT_0B =>
    X"A63A2C98BD68A190ECE31E3705A9378C9D1E8552B3E7E5EE00A8D013C727A363",
    INIT_0C =>
    X"825E50D3C337E391D285B3E810E3A0D7685653D94D3E71908B1A0B41E592532B",
    INIT_0D =>
    X"37BBD94017A3516B4967BD75065601C1A07433BCD239DE86D92D4DA53D55B981",
    INIT_0E =>
    X"3E764373E02864893E1301E208892D2569D1ED0979D06EC0000928245A49AA11",
    INIT_0F =>
    X"AEA8387C19D3BAD3DED01AE68780851E039D6569CD94656616126E516764E078",
    INIT_10 =>
    X"9107D66D37276715944658B74A886219E8245299D83648117887622ACD2C35C5",
    INIT_11 =>
    X"397370A02C1787D6B595D4A5AC755CBE31E689D3051A08405ECC1E99030855C1",
    INIT_12 =>
    X"7331991EA02E2DEA3D652D24661C90E9D16940AA1AAE91399003462DD631AC94",
    INIT_13 =>
    X"A2CB044E7A59C17279009084672932CC3533E4EBED516AC7721ECBD266883CD1",
    INIT_14 =>
    X"A1765046C93423316DD2B122D28AD0DCDD103BA92EE602D8422012220C91032D",
    INIT_15 =>
    X"4592C5C36758B8D5D1C023E6382A362A9D368B2D4A55B635A832D51AA42728CE",
    INIT_16 =>
    X"EE8C72A89284A695C3D69DB5902E5319A2EA837D7609ACA4AA6CA489B7D302B1",
    INIT_17 =>
    X"5C3E3E9E9C0878C8AC6ECBE615836CCB43C1A5E4603224A7B01C4D30BA613848",
    INIT_18 =>
    X"70CE6A81349A33784ED013CDB6E62C469B471315970CB17B7589025586833A6C",
    INIT_19 =>
    X"05540E35E27C1277A11C0E6D17D114926B534032D816C57B7B11B524306498ED",
    INIT_1A =>
    X"708D82706D0B19581D1A8E58BCE5D5296C61CA6022E55BDD1DD16162094D4EED",
    INIT_1B =>
    X"2A693B87804ABE0A13AA3AB724B2A791C18DA76921DC35228D5EC1D9763C6725",
    INIT_1C =>
    X"D990AB41C6BD350363DB64D013484D6A59A0065A6DE67C00A7A256C28001D80B",
    INIT_1D =>
    X"E820A2025B1818A1A471AC876C288829A0594A85445B1B7834C73D5434DEC9E5",
    INIT_1E =>
    X"5247B680E5856510890DEB25C1835930256A2CEE12857D397DDE185EB277186D",
    INIT_1F =>
    X"BA60A017C650389739C753904943A841538E0670A65E83AC4043790C30E6669A",
    INIT_20 =>
    X"246C9E9DCB5D2D4CC66AA13C65AC49401B640926975ED881D5BE04838EA68123",
    INIT_21 =>
    X"3B98B3398E27C17667801A7AB02CA95E8756A83B02A24CD777936336AB82B0B7",
    INIT_22 =>
    X"EAB1A46DD0A426D85C40E307D858ADC1608B8CCDECD0CDC508129ED37712EA08",
    INIT_23 =>
    X"906539C37E94749A9EE3587351CB4DD87E382834ACABCB5C1B805D840C3C22A0",
    INIT_24 =>
    X"23BBD272324592E18081970242A3BA026693A37DA93CD1AC2CB3A7A8186951B5",
    INIT_25 =>
    X"BA4CD0D6ABC1C9948551DAA39CDA85BE7D666853B026573D5A6149D83C83230B",
    INIT_26 =>
    X"E82DE897419589BE836419AC18918889C2D9A1EACDE94ABD93E92A845B9D6C00",
    INIT_27 =>
    X"6061B4CDA55B0B32779A270D19D8AA0531A0C89BA1E17A4016A002ADD2235777",
    INIT_28 =>
    X"9CB86AED9549A707235322D3C5463796DE311DC541AB2CD0912CDE44B8DDCE71",
    INIT_29 =>
    X"B43024155B29AC819D78944DA8574EED8A0E357072CEE0916AE57D686471EE3C",
    INIT_2A =>
    X"DD6C8048AE468CD92990C481D7C1EB6ED8681E022A608828D190B171463592C4",
    INIT_2B =>
    X"11ED653750DC76D8B653769DE776DCA4279A0DC428ABBE7934917B70EB280301",
    INIT_2C =>
    X"E679CCAB8C41DA9B3C68E037E62CCDA28AC3B962EAB29EB840A2A6648C910749",
    INIT_2D =>
    X"B3E18D758E9B71D12B73BB60DEB04C7951BC8D98BD468207AC1C06C1C04DB702",
    INIT_2E =>
    X"B2A81000A55C3B44BE30D942E9E6068DA8BE420998BE13EB6813059B03C71897",
    INIT_2F =>
    X"CD935A639274D03D83B1597E77BA72725D6543414079037792295D6D3ED02B6E",
    INIT_30 =>
    X"D3EB4528A277C02A53B405BAC8C291B90D86A83AAB0C0659A64D9A1722B2E7D6",
    INIT_31 =>
    X"A52B397960E0BB813D650DEDDE8934E6E7CC0CD738835C83BD0670310A89035E",
    INIT_32 =>
    X"3008A539DA3B2B0CC660AB7C3335BD7B4E7851EDBB1D82494D09EC22011E5C59",
    INIT_33 =>
    X"867370158A154636585837376EB91D7B5A3CA037846706665D94A89DC25E6590",
    INIT_34 =>
    X"52B23273DD410DD802E4D86211B4866A46D719B12187B7C9E21DC9D816CA43A9",
    INIT_35 =>
    X"494494A876798145C8D4C19D2C4828D2698C994356323A4A3444ED9D03D67DD9",
    INIT_36 =>
    X"3560BB813222D28614B06885C11BADB5481ADE0402EE672076DD96935A02EBAC",
    INIT_37 =>
    X"747673B5ACB7B60DC6B8BA3B99612D36B82D479503719C6C0BBE9E9BB0AB5C50",
    INIT_38 =>
    X"7E5B3037525C8044D085A4C294204C32786478A4D7D08D1C2E91486C5CCA00DA",
    INIT_39 =>
    X"72E9D33644047E9C975DC8EACD22A7C1BCA17E08AC475B5382D57712DD5B9495",
    INIT_3A =>
    X"E1ECEA16C38C7B91004A1DB9621DEBE7AAAA53319860BAB59736958915AE8110",
    INIT_3B =>
    X"06D6C17D9EA65C31707CE127460640BE179626E758C41A5D117E85748E79770D",
    INIT_3C =>
    X"46746B699DBE74D2582A669821825634984163E8C49B48494A71122A135CA2EC",
    INIT_3D =>
    X"E63E9317D9678103A976196BE59BB75816A6140C68E95221567E103CB184E5A1",
    INIT_3E =>
    X"55BADDCBB01705A7A516A9EE5261952711D56002138E300DC5A8068ACE48243E",
    INIT_3F =>
    X"DA2A16DDDC46264E61237022D97510AA6AC244EA0A66C6D62A0A934EDB27C9CB",
    -- The next set of INITP_xx are for the parity bits
    -- Port A Address 0 to 1023, Port B Address 0 to 255
    INITP_00 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    INITP_01 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    -- Port A Address 1024 to 2047, Port B Address 256 to 511
    INITP_02 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    INITP_03 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    -- Port A Address 2048 to 3071, Port B Address 512 to 767
    INITP_04 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    INITP_05 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    -- Port A Address 3072 to 4095, Port B Address 768 to 1023
    INITP_06 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    INITP_07 =>
    X"0000000000000000000000000000000000000000000000000000000000000000")
    port map (
    DOA => DATA_toMUX, -- Port A 4-bit Data Output
    DOB => DATA_toSER, -- Port B 16-bit Data Output
    DOPB => open, -- Port B 2-bit Parity Output
    ADDRA => ADDRESS_MUX, -- Port A 12-bit Address Input
    ADDRB => ADDRESS_SEND, -- Port B 10-bit Address Input
    CLKA => CLK_MUX, -- Port A Clock
    CLKB => CLKX1, -- Port B Clock
    DIA => "1111", -- Port A 4-bit Data Input
    DIB => "1111111111111111", -- Port B 16-bit Data Input
    DIPB => "11", -- Port-B 2-bit parity Input
    ENA => EN_toMUX, -- Port A RAM Enable Input
    ENB => EN_SEND, -- PortB RAM Enable Input
    SSRA => RESET_toMUX, -- Port A Synchronous Set/Reset Input
    SSRB => RESET_SEND, -- Port B Synchronous Set/Reset Input
    WEA => '0', -- Port A Write Enable Input
    WEB => '0' -- Port B Write Enable Input
    );


    end Behavioral;


    --BRAM_RECEIVE-FILE :
    *************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity BRAM_RECEIVE is
    port(
    DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
    Data Output
    DATA_fromDES : in std_logic_vector(15 downto 0); -- Port B
    16-bit Data Intput
    ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
    Address Input
    ADDRESS_RECEIVE: in std_logic_vector(9 downto 0); -- Port B
    10-bit Address Input
    CLK_MUX : in std_logic; -- Port A Clock
    CLKX1_PS : in std_logic; -- Port B Clock (PS: phase-shifted)
    Verzögerung des DUTs
    EN_toMUX : in std_logic; -- Port A RAM Enable Input
    EN_RECEIVE : in std_logic; -- PortB RAM Enable Input
    RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
    Input
    WRITE_ENABLE : in std_logic
    );
    end BRAM_RECEIVE;

    architecture Behavioral of BRAM_RECEIVE is

    begin

    RAMB16_S4_S18_instBRAM_R : RAMB16_S4_S18
    generic map (
    INIT_A => X"0", -- Value of output RAM registers on Port A at
    startup
    INIT_B => "000000000000000000", -- Value of output RAM registers
    on Port B at startup
    SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
    SRVAL_B => "000000000000000000", -- Port B ouput value upon SSR
    assertion
    WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
    NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
    NO_CHANGE
    SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING",
    "GENERATE_X_ONLY", "ALL
    -- The following INIT_xx declarations specify the initial
    contents of the RAM
    -- Port A Address 0 to 1023, Port B Address 0 to 255
    INIT_00 =>
    X"0B3590A1A174768987DBEA2C0A79BC3074933CE64B47E2B94839CABE379ECC71",
    INIT_01 =>
    X"757BD429738DA3B5A0B9494ED34701908332C6C3E6E7B76EA71E874BD75ACC6D",
    INIT_02 =>
    X"EE5D23172975488DE0E4C2CBB8107AC1E5944BB3DA3C0EB51318D2EA77138A60",
    INIT_03 =>
    X"579DB42A34470D66B69964892EE560544E7403D0487D9CA8010837BDAD631005",
    INIT_04 =>
    X"2399A631B2036C2EB2AC8E53ABE27DEDBC5188D14B3A3392557ABE3738321422",
    INIT_05 =>
    X"C8090DEA9B8B3E883E6489635B31E416468ED9687A5B358874275327AE030008",
    INIT_06 =>
    X"731B6C3308B38B6C0D326BB6D3E06770238588261AA155D9C1C4A5A3D13429C7",
    INIT_07 =>
    X"C918863BBECA868E6B3C85928E1CBDB6C38E6CA474D1679D512EC630D4714340",
    INIT_08 =>
    X"10566A52029BCCB3908DEDE5BCD66D8A0B9A8EA8209E86E46846C0B2809843B9",
    INIT_09 =>
    X"859E4E4D966313D79E3D6468BE556E5D2E86E7DED1E6BCA47B8A969969AB0356",
    INIT_0A =>
    X"5C8D1CEBB5E6E922785C707BED2633EB00BD915C902A056B5D06ED024914310A",
    INIT_0B =>
    X"550D1E5B4D9A10859202097C13533CDD9A9760BDB0D15C5A8404AC334CE35E32",
    INIT_0C =>
    X"134CB61CC92880A2A3A07045E587DECE9B9211B70944E4A2521E0940AC9113E3",
    INIT_0D =>
    X"EC82D7253C621B02A01DB21467D4A940EAE7491CE779070CDD17C0180DA6E7D6",
    INIT_0E =>
    X"7515EB022A8849ACA9A5C75251862103763144ADDB5AD12D599A57A120E4223B",
    INIT_0F =>
    X"24A096D40000CCBC1AAB8A64746725837098DE73BDBDC5324B670B7E29240533",
    INIT_10 =>
    X"D53CE81960775D439C74ED1D2754229BD42D46DDB9950CE2859B7B8241166535",
    INIT_11 =>
    X"A7A790B1BED30631AB5EC5B9BDB59EAB0CAC4E3D88EDDD6A1D182AADA54B3D4A",
    INIT_12 =>
    X"251CBA57185B5D4668AB34A466D81970AD1CEBE3AC0A187E3EB74187A6AC2CDA",
    INIT_13 =>
    X"7EEDE77DD75437D53E9207A92BBC67914A41A408566072127EA3B2DEB9D53C06",
    INIT_14 =>
    X"E0D1C599386389B6B54BA14C2B789E3A979811CB416933A62937ADD04EB189AB",
    INIT_15 =>
    X"464662DA8020A74474A87C2A52A407C41CE69291558C3937C34C86DACA5D2775",
    INIT_16 =>
    X"16A4643C5E97803607E2864BE61C5BA3014B497CE6128D18A6E77C582681A4A8",
    INIT_17 =>
    X"C6A37A99254E0DD0462D39BEC8034DCECCDAE6BB732134CD59878443E675A089",
    INIT_18 =>
    X"739914A602CD098E674EE2A54AD370EC953A4ADCB8D35EA090394325DC72B3CC",
    INIT_19 =>
    X"63A805EACD00E597D70C8AB5A681BA8294272390BE1C33BC6D1725509C23EDAC",
    INIT_1A =>
    X"B144B8C3B9B62748CE689E60B1C5A36DCE9E268D484B9154976ADAE407567E18",
    INIT_1B =>
    X"D4077889214A840C1A88E3CADE1A880EC65E97784521D515C37D575B0ABEA0E1",
    INIT_1C =>
    X"41403DE8985618E4D9D71A8856371D92C76DBA6E890929A021DCBA19051A60C4",
    INIT_1D =>
    X"6DACB5AA04550902A834C0B4031A04A6BC0DB5149DCA4BB2B9C7EE058586885C",
    INIT_1E =>
    X"DD3DE0AB96E7EED41168A0EA91E9D0715A48DA1C947D0383DD73A5BBECE04E38",
    INIT_1F =>
    X"6864B20C2D189816EC938CB71656978122D7781DA562ADB21CAED81AC5E2A53A",
    INIT_20 =>
    X"B2236BB14A6770370DED633D27ECB88C50622A3D7D77EB87A7E0379662DBCA98",
    INIT_21 =>
    X"289EC1D363D15E3B38601D02A13523815674B6B59335BB8815309DA65EC8381B",
    INIT_22 =>
    X"3EBAE3DE211C45498C23112D6765593CE3B6CE3C436C2D16A8E84BD7D4968C8B",
    INIT_23 =>
    X"DC91077562070CDC3DB6CECE4776AD272663D3467C2C162C06041C9017714181",
    INIT_24 =>
    X"2E1715E9C1C88E9A1D23B47E7EB3CA8C1D71DB28E4A5AE90D3E6A8D4D22D34E3",
    INIT_25 =>
    X"62C6327D4A632400B881AC5C789708D4434B51E6A006C582B3201913B742A06C",
    INIT_26 =>
    X"34BB8C76C978EC4BB4092BD8645E5B7B7BA4465D0D7038ADE925D8C17133E249",
    INIT_27 =>
    X"02E14B2469EA143810931358BBE92B3917948E026B91B8207BBD18CCB41B0536",
    INIT_28 =>
    X"B15BDDB22ED3989D6A58D0A63D1D1CEBDB8340E917447B31950EC8C347BB0D17",
    INIT_29 =>
    X"66052893E55DC45710706D8E3CBBD618CA2D67162DE6E8EE0AD2049BA2B46777",
    INIT_2A =>
    X"977285925069B73AC154A8ECE130AD752A897E48AC719623504164B83C76E0C5",
    INIT_2B =>
    X"89B4BE42541A847B0223922554D451094A635DE9544205622B36D293799B11A1",
    INIT_2C =>
    X"79B9CD247A7973EA5B762E132C955D0901C3AE80C74CB38CC58C8EBDD4DBE0E3",
    INIT_2D =>
    X"2C92774BAA711678215E1A62B54395664089B050AC764D18463D6E025888103D",
    INIT_2E =>
    X"A94C2C9C964974C62ADC092CC62AA01B53814B569290A0DE47C61E084D49BEDC",
    INIT_2F =>
    X"7BCBA95019C7D167B6A6BC80584578582C9389EE1757C4D506249C2BBAD9BE9C",
    INIT_30 =>
    X"81211DC8374AD2D8AAAE52068C386219D13749970D68D60B97CE1ED587786C32",
    INIT_31 =>
    X"CE616EA9658D4B3724958B4DCB9C7C308929AC8BA7C7B048BE8DD12D31E09A57",
    INIT_32 =>
    X"CAE0555E5C4AED028CE36ECE5CAEA51E5C790CD086D69513970B538117ED91D4",
    INIT_33 =>
    X"79EE0487DC6BC15325DE54501B4E6A86C36291590CAAC1D2300BB75E382066E0",
    INIT_34 =>
    X"48CC0E891D2146B3A1524249B64321EA29EA7A0ECB60066E7AA0CE99035A2B53",
    INIT_35 =>
    X"ACA96E9CDDDEB7CBE385827B481BC8454A6D97117CBAA7E64421E5D9E6C24946",
    INIT_36 =>
    X"4CC35D2066B48B1545E9393DC665EDC8EA458C9753EC40910935507B6A3C8582",
    INIT_37 =>
    X"5C0279A105462789E9AC29566D527E65324A26ECC674D31A3E8A7CED5ACD525D",
    INIT_38 =>
    X"888551B655EC6E6930C940B71B755A7E3EEC888729349B981ECEE2C4A9437681",
    INIT_39 =>
    X"A13539E0D35A409D50E07EACE4D86067D219A133EEA04CBBB8533356EAD153AC",
    INIT_3A =>
    X"D7AE7AA282818050A618B3321458D9190A9C8274402C18C7ED2901487E7D36B0",
    INIT_3B =>
    X"05B4E9256519A36309D976C500ADE14590D51A175C3D6B68351424C15A8462C5",
    INIT_3C =>
    X"9BB38E3071EE97A40156A5AD5DBE49E757E16D1BD195DEC7C7A7D79D488AB5AA",
    INIT_3D =>
    X"13539E09B9339078A1151363907AA370AB6A49B1366A6889DCD2AD14741DA981",
    INIT_3E =>
    X"765B0AED38804B7D11A8CC166E97A3A3676AE7A1C656A80116A394203D03D4B8",
    INIT_3F =>
    X"35061DB65D374DB727B6AA34C3ADA0E8D6A4A00489978B220AD0214A73C5D8E9")
    port map (
    DOA => DATA_toMUX, -- Port A 4-bit Data Output
    DOB => open, -- Port B 16-bit Data Output
    DOPB => open, -- Port B 2-bit Parity Output
    ADDRA => ADDRESS_MUX, -- Port A 12-bit Address Input
    ADDRB => ADDRESS_RECEIVE, -- Port B 10-bit Address Input
    CLKA => CLK_MUX, -- Port A Clock
    CLKB => CLKX1_PS, -- Port B Clock
    DIA => "1111", -- Port A 4-bit Data Input
    DIB => DATA_fromDES, -- Port B 16-bit Data Input
    DIPB => "11", -- Port-B 2-bit parity Input
    ENA => EN_toMUX, -- Port A RAM Enable Input
    ENB => EN_RECEIVE, -- PortB RAM Enable Input
    SSRA => RESET_toMUX, -- Port A Synchronous Set/Reset Input
    SSRB => '0', -- Port B Synchronous Set/Reset Input
    WEA => '0', -- Port A Write Enable Input
    WEB => WRITE_ENABLE -- Port B Write Enable Input
    );


    end Behavioral;
     
    , Dec 18, 2006
    #1
    1. Advertising

  2. Hi Thomas.

    There are a multitude of reasons why this might not work, not necessarily
    due to the VHDL being wrong.

    As you say you've tested in stand-alone mode, does that you verified the
    function in real hardware?

    Or did you just simulate?

    Ben

    <> wrote in message
    news:...
    Greetings to all !

    I started programming with VHDL two months ago. Now I want to implement
    a project on a Spartan 3 (XC3S50 VQ100). The software I´m using is the
    ISE Webpack 8.2.03i (Application Version: I.34).
    This project is later supposed to be a bit error testing instance in
    combination with an Microcontroller that is used to read out an compare
    the sended and received data from the block RAMs of the Spartan 3.
    I tested the components I used as standalone-designs and they all seem
    to function but when I try to make one pice of all designs the FPGA
    doesn´t show any expected behaviour at all-even some simple LED I
    integrated in the design to indicate if the clock is active don't start
    flashing.

    Although i know it's probably not the smartest way to ask for help but
    as I need this project to function for my thesis i have no other ideas
    than posting the whole code - any words are very appreciated (the
    comments are in german and not so important)!!!

    p.s.: It would also help if someone would just copy and paste this code
    into a new projektfile to find out if it´s running(simplest
    indication: the State LED_Z0 should be on and the LED_Z1 should be
    flashing) on his hardware.

    #UCF - File :
    ****************************************************************************************************

    NET "CLK_IN" LOC = "P36" | IOSTANDARD = LVTTL ; #Takt vom
    Meltemi-Board (66 MHz)

    NET "CLK_fromMC" LOC = "P39" | IOSTANDARD = LVTTL ;#Takt com MC
    NET "DATA_toMC<0>" LOC = "P30" | IOSTANDARD = LVTTL
    ;#Datenleitungen
    NET "DATA_toMC<1>" LOC = "P32" | IOSTANDARD = LVTTL ;
    NET "DATA_toMC<2>" LOC = "P34" | IOSTANDARD = LVTTL ;
    NET "DATA_toMC<3>" LOC = "P35" | IOSTANDARD = LVTTL ;
    NET "MC_READY" LOC = "P43" | IOSTANDARD = LVTTL ;#MC ist fertig mit
    Auslesen
    NET "MC_READ" LOC = "P44" | IOSTANDARD = LVTTL ;#MC soll mit Auslesen
    beginnen

    NET "INDICATION_MUXtoMC<1>" LOC = "P47" | IOSTANDARD = LVTTL ;
    NET "INDICATION_MUXtoMC<0>" LOC = "P59" | IOSTANDARD = LVTTL ;

    NET "LED_Z0" LOC = "P72" | IOSTANDARD = LVTTL ;
    NET "LED_Z1" LOC = "P50" | IOSTANDARD = LVTTL ;
    NET "LED_Z2" LOC = "P55" | IOSTANDARD = LVTTL ;
    ###############LVDS-Kanäle###############################
    NET "LVDS_Nr" LOC = "P88" | IOSTANDARD = LVDSEXT_25 ;#r: receive
    NET "LVDS_Ns" LOC = "P90" | IOSTANDARD = LVDSEXT_25 ;#s: send
    NET "LVDS_Pr" LOC = "P87" | IOSTANDARD = LVDSEXT_25 ;
    NET "LVDS_Ps" LOC = "P89" | IOSTANDARD = LVDSEXT_25 ;

    ################TASTER####################################
    NET "BUTTON" LOC = "P21" | IOSTANDARD = LVTTL ;#USERSTART

    --Topmodule -File:
    **********************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity TOPMODULE is
    generic(
    WAIT_WIDTH_USERSTART : positive := 28;
    WAIT_WIDTH_MC_READY : positive := 10;
    CNT_WIDTH : positive := 25
    );
    Port ( CLK_IN : in STD_LOGIC;
    MC_READY : in STD_LOGIC;
    BUTTON : in std_logic;
    LVDS_Pr : in STD_LOGIC; --receive
    LVDS_Nr : in STD_LOGIC;
    LVDS_Ps : out STD_LOGIC;--send
    LVDS_Ns : out STD_LOGIC;
    LED_Z0 : out STD_LOGIC;
    LED_Z1 : out STD_LOGIC;
    LED_Z2 : out STD_LOGIC;
    DATA_toMC : out STD_LOGIC_VECTOR (3 downto 0);
    MC_READ : out STD_LOGIC;
    CLK_fromMC : in std_logic;
    INDICATION_MUXtoMC : out std_logic_vector(1 downto 0)
    );
    end TOPMODULE;

    architecture Behavioral of TOPMODULE is

    component STATE_MACHINE
    port(CLKX1 : in std_logic;
    USER_START : in std_logic;
    ADDRESS_CONTROL_FINISH : in std_logic;
    MC_READY : in std_logic;
    BRAM1_EN_toMUX : out std_logic; --Ausgangssignale zu BRAM1
    BRAM1_EN_SEND : out std_logic;
    BRAM1_RESET_toMUX : out std_logic;
    BRAM1_RESET_SEND : out std_logic;
    BRAM2_EN_RECEIVE : out std_logic; --Ausgangssignale zu BRAM2
    BRAM2_EN_toMUX : out std_logic;
    BRAM2_RESET_toMUX : out std_logic;
    BRAM2_WRITE_EN : out std_logic;
    MUX_RESET : out std_logic;
    DES_EN : out std_logic;
    SER_NEN : out std_logic;
    SER_RESET : out std_logic;
    ADDR_CONTROL_RESET_NEN : out
    std_logic;--ADDRESS_CONTROL_RESET_(and)NotENable
    MC_READ : out std_logic;
    LED_Z0 : out std_logic; --die LEDs signalisieren den aktuellen
    Zustand
    LED_Z2 : out std_logic--;
    );
    end component;

    component ADDRESS_CONTROL
    generic(
    ADDRESS_WIDTH : positive := 10
    );
    Port ( CLKX1 : in std_logic;
    RESET_NEN : in STD_LOGIC;
    ADDR_BRAM1 : out STD_LOGIC_VECTOR (9 downto 0);
    ADDR_BRAM2 : out STD_LOGIC_VECTOR (9 downto 0);
    FINISH : out std_logic
    );
    end component;

    component SER16to1
    Port ( CLKX8 : in std_logic; --8facher Takt (bezogen auf den Takt des
    16 Bit breiten Datenbus)
    CLKX8_180 : in std_logic; --8facher Takt invertiert
    RESET : in std_logic; --Reseteingang
    NotENABLE : in std_logic;
    DATA_PARALLEL : in std_logic_vector(15 downto 0);
    ODATA_LVDSP : out std_logic;
    ODATA_LVDSN : out std_logic);
    end component;

    component DES1to16
    Port ( ENABLE : in std_logic; --mit DCM_LOCKED verbinden
    IDATA_LVDSP : in std_logic;
    IDATA_LVDSN : in std_logic;
    CLKX8 : in STD_LOGIC;
    CLKX8_180 : in STD_LOGIC;
    CLKX1 : in STD_LOGIC;
    DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0)
    );
    end component;

    component MUX
    generic(
    DATA_WIDTH: positive := 4;--Breite des Datenbusses
    ADRESS_WIDTH_toMC: positive := 12;
    CONTROL_WIDTH: positive := 2--Anzahl der Steuerleitungen
    );
    Port ( DATA1 : in STD_LOGIC_VECTOR (3 downto 0);--Daten von BRAM1
    DATA2 : in STD_LOGIC_VECTOR (3 downto 0);--Daten von BRAM2
    DATA_OUT : out STD_LOGIC_VECTOR (3 downto 0);--Datenbus zum
    Mikrocontroller
    ADRESS1 : out std_logic_vector(11 downto 0);--Adressbusse zu den
    BRAMs
    ADRESS2 : out std_logic_vector(11 downto 0);
    RESET : in std_logic;--asynchrones Resetsignal von der
    State-Machine
    INDICATION : out STD_LOGIC_VECTOR(1 downto 0);--Kontrollbus
    zum Mikrocontroller
    CLK_extMC : in STD_LOGIC;--Auslesetakt für die BRAMs (vom
    Mikrocontroller generiert)
    CLK_fromMC :eek:ut STD_LOGIC
    );
    end component;

    component BRAM_SEND
    port(
    DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
    Data Output
    DATA_toSER : out std_logic_vector(15 downto 0); -- Port B
    16-bit Data Output
    ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
    Address Input
    ADDRESS_SEND: in std_logic_vector(9 downto 0); -- Port B 10-bit
    Address Input
    CLK_MUX : in std_logic; -- Port A Clock
    CLKX1 : in std_logic; -- Port B Clock
    EN_toMUX : in std_logic; -- Port A RAM Enable Input
    EN_SEND : in std_logic; -- PortB RAM Enable Input
    RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
    Input
    RESET_SEND : in std_logic -- Port B Synchronous Set/Reset Input
    );
    end component;

    component BRAM_RECEIVE
    port(
    DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
    Data Output
    DATA_fromDES : in std_logic_vector(15 downto 0); -- Port B
    16-bit Data Intput
    ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
    Address Input
    ADDRESS_RECEIVE: in std_logic_vector(9 downto 0); -- Port B
    10-bit Address Input
    CLK_MUX : in std_logic; -- Port A Clock
    CLKX1_PS : in std_logic; -- Port B Clock (PS: phase-shifted)
    Verzögerung des DUTs
    EN_toMUX : in std_logic; -- Port A RAM Enable Input
    EN_RECEIVE : in std_logic; -- PortB RAM Enable Input
    RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
    Input
    WRITE_ENABLE : in std_logic
    );
    end component;


    component GENERATE_CLOCK
    Port ( CLKIN_IN : in std_logic; --Oszillator mit 66 MHz
    (meltemi: P36)
    CLKDV_OUT : out std_logic; --33 Mhz Takt
    CLKFX_OUT : out std_logic; --264 MHz Takt
    CLKFX180_OUT : out std_logic
    );
    end component;


    signal CLKX1, CLKX8, CLKX8_180 : std_logic;
    signal ADDRESS_CONTROL_FINISH, BRAM1_EN_SEND, BRAM1_RESET_toMUX,
    BRAM1_RESET_SEND : std_logic;
    signal BRAM2_EN_RECEIVE, BRAM2_RESET_toMUX, BRAM2_WRITE_EN, MUX_RESET :
    std_logic;
    signal DES_EN, SER_NEN, SER_RESET, ADDR_CONTROL_RESET_NEN : std_logic;
    signal ADDR_BRAM1, ADDR_BRAM2 : std_logic_vector(9 downto 0);
    signal DATA_toSER16to1, DATA_fromDES1to16 : std_logic_vector(15 downto
    0);
    signal DATA_toMUX_BRAM_S, DATA_toMUX_BRAM_R : std_logic_vector(3 downto
    0);
    signal ADDRESS_BRAM_SEND, ADDRESS_BRAM_RECEIVE : std_logic_vector(11
    downto 0);
    signal BRAM1_EN_toMUX, BRAM2_EN_toMUX : std_logic;

    signal USERSTART : std_logic := '0';

    signal CLK_fromMC_buffered : STD_LOGIC;


    --Taster :
    --Tatser1 :
    signal SHIFT_PB1 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
    signal BUTTON_DEBOUNCED1 : std_logic := '0';
    signal LEVEL1 : std_logic := '0';


    --CLK-Indication :
    signal CNT : std_logic_vector(CNT_WIDTH-1 downto 0) := (others => '0');
    constant MAX_CNT : std_logic_vector(CNT_WIDTH-1 downto 0) := (others =>
    '1');
    signal LEVEL : std_logic := '0';


    begin

    inst_GC : GENERATE_CLOCK
    port map(
    CLKIN_IN => CLK_IN, --externer Takt
    CLKDV_OUT => CLKX1, --33 Mhz Takt
    CLKFX_OUT => CLKX8, --264 MHz Takt
    CLKFX180_OUT => CLKX8_180--CLKX8 um 180° phasenverschoben

    );

    inst_SM : STATE_MACHINE
    port map(
    CLKX1 => CLKX1,
    USER_START => USERSTART,
    ADDRESS_CONTROL_FINISH => ADDRESS_CONTROL_FINISH,
    MC_READY => MC_READY,--MC herausgenommen
    BRAM1_EN_toMUX => BRAM1_EN_toMUX, --Ausgangssignale zu BRAM1
    BRAM1_EN_SEND => BRAM1_EN_SEND,
    BRAM1_RESET_toMUX => BRAM1_RESET_toMUX,
    BRAM1_RESET_SEND => BRAM1_RESET_SEND,
    BRAM2_EN_RECEIVE => BRAM2_EN_RECEIVE, --Ausgangssignale zu BRAM2
    BRAM2_EN_toMUX => BRAM2_EN_toMUX,
    BRAM2_RESET_toMUX => BRAM2_RESET_toMUX,
    BRAM2_WRITE_EN => BRAM2_WRITE_EN,
    MUX_RESET => MUX_RESET,
    DES_EN => DES_EN,
    SER_NEN => SER_NEN,
    SER_RESET => SER_RESET,
    ADDR_CONTROL_RESET_NEN =>
    ADDR_CONTROL_RESET_NEN,--ADDRESS_CONTROL_RESET_(and)NotENable
    MC_READ => MC_READ,
    LED_Z0 => LED_Z0, --die LEDs signalisieren den aktuellen Zustand
    LED_Z2 => LED_Z2
    );

    inst_AC : ADDRESS_CONTROL
    port map(
    CLKX1 => CLKX1,
    RESET_NEN => ADDR_CONTROL_RESET_NEN,
    ADDR_BRAM1 => ADDR_BRAM1, --BRAM_SEND
    ADDR_BRAM2 => ADDR_BRAM2, --BRAM_RECEIVE
    FINISH => ADDRESS_CONTROL_FINISH
    );

    inst_SER : SER16to1
    port map(
    CLKX8 => CLKX8, --8facher Takt (bezogen auf den Takt des 16 Bit
    breiten Datenbus)
    CLKX8_180 => CLKX8_180, --8facher Takt invertiert
    RESET => SER_RESET, --Reseteingang
    NotENABLE => SER_NEN,
    DATA_PARALLEL => DATA_toSER16to1,
    ODATA_LVDSP => LVDS_Ps,
    ODATA_LVDSN => LVDS_Ns
    );

    inst_DES : DES1to16
    port map(
    ENABLE => DES_EN, --mit DCM_LOCKED verbinden
    IDATA_LVDSP => LVDS_Pr,
    IDATA_LVDSN => LVDS_Nr,
    CLKX8 => CLKX8,
    CLKX8_180 => CLKX8_180,
    CLKX1 => CLKX1,
    DATA_OUT => DATA_fromDES1to16
    );

    inst_MUX : MUX
    port map(
    DATA1 => DATA_toMUX_BRAM_S,--Daten von BRAM1
    DATA2 => DATA_toMUX_BRAM_R,--Daten von BRAM2
    DATA_OUT => DATA_toMC,--Datenbus zum Mikrocontroller
    ADRESS1 => ADDRESS_BRAM_SEND,--Adressbusse zu den BRAMs
    ADRESS2 => ADDRESS_BRAM_RECEIVE,
    RESET => MUX_RESET,--asynchrones Resetsignal von der State-Machine
    INDICATION => INDICATION_MUXtoMC,--Kontrollbus zum
    Mikrocontroller
    CLK_extMC => CLK_fromMC--Auslesetakt für die BRAMs (vom
    Mikrocontroller generiert)
    );

    inst_BRAM_S : BRAM_SEND --BRAM1
    port map(
    DATA_toMUX => DATA_toMUX_BRAM_S, -- Port A 4-bit Data Output
    DATA_toSER => DATA_toSER16to1, -- Port B 16-bit Data Output
    ADDRESS_MUX => ADDRESS_BRAM_SEND, -- Port A 12-bit Address Input
    ADDRESS_SEND => ADDR_BRAM1, -- Port B 10-bit Address Input
    CLK_MUX => CLK_fromMC_buffered, -- Port A Clock
    CLKX1 => CLKX1, -- Port B Clock
    EN_toMUX => BRAM1_EN_toMUX, -- Port A RAM Enable Input
    EN_SEND => BRAM1_EN_SEND, -- PortB RAM Enable Input
    RESET_toMUX => BRAM1_RESET_toMUX, -- Port A Synchronous
    Set/Reset Input
    RESET_SEND => BRAM1_RESET_SEND -- Port B Synchronous Set/Reset
    Input
    );

    inst_BRAM_R : BRAM_RECEIVE
    port map(
    DATA_toMUX => DATA_toMUX_BRAM_R, -- Port A 4-bit Data Output
    DATA_fromDES => DATA_fromDES1to16, -- Port B 16-bit Data
    Intput
    ADDRESS_MUX => ADDRESS_BRAM_RECEIVE, -- Port A 12-bit Address
    Input
    ADDRESS_RECEIVE => ADDR_BRAM2, -- Port B 10-bit Address Input
    CLK_MUX => CLK_fromMC_buffered, -- Port A Clock
    CLKX1_PS => CLKX1, -- Port B Clock (PS: phase-shifted)
    Verzögerung des DUTs
    EN_toMUX => BRAM2_EN_toMUX, -- Port A RAM Enable Input
    EN_RECEIVE => BRAM2_EN_RECEIVE, -- PortB RAM Enable Input
    RESET_toMUX => BRAM2_RESET_toMUX, -- Port A Synchronous
    Set/Reset Input
    WRITE_ENABLE => BRAM2_WRITE_EN
    );



    --CLK-Indication :
    CLK_indication: process(CLKX1)
    begin
    if (CLKX1'event and CLKX1 = '1') then
    if CNT = MAX_CNT then
    LEVEL <= not LEVEL;
    CNT <= (others => '0');
    else
    CNT <= CNT +1;
    end if;
    end if;
    end process;

    LED_Z1 <= LEVEL;
    --LED_Z1 <= '1';
    ----Taster1 :
    DEBOUNCE1: process(CLKX1)
    begin
    if (CLKX1'event and CLKX1 = '1') then
    -- Use a shIFt register to filter switch contact bounce
    SHIFT_PB1(2 downto 0) <= SHIFT_PB1(3 downto 1);
    SHIFT_PB1(3) <= BUTTON;
    if SHIFT_PB1(3 downto 0) = "0000" then
    BUTTON_DEBOUNCED1 <= '0';
    else
    BUTTON_DEBOUNCED1 <= '1';
    end if;
    end if;
    end process;

    SWITCH1: process(BUTTON_DEBOUNCED1)
    begin
    if (BUTTON_DEBOUNCED1'event and BUTTON_DEBOUNCED1 = '1') then
    LEVEL1 <= not LEVEL1;
    end if;
    end process;

    USERSTART <= LEVEL1;


    end Behavioral;

    --GENERATE_CLOCK-FILE :
    *********************************************************************************

    library ieee;
    use ieee.std_logic_1164.ALL;
    use ieee.numeric_std.ALL;
    library UNISIM;
    use UNISIM.Vcomponents.ALL;

    --konfiguriert für einen Eingangstakt der Frequenz 66 MHz

    entity GENERATE_CLOCK is
    port ( CLKIN_IN : in std_logic; --Oszillator mit 66 MHz
    (meltemi: P36)
    CLKDV_OUT : out std_logic; --33 Mhz Takt
    CLKFX_OUT : out std_logic; --264 MHz Takt
    CLKFX180_OUT : out std_logic
    );-- = '1' -> DCM eingeschwungen
    end GENERATE_CLOCK;

    architecture BEHAVIORAL of GENERATE_CLOCK is

    component BUFG
    port ( I : in std_logic;
    O : out std_logic);
    end component;

    component IBUFG
    port ( I : in std_logic;
    O : out std_logic);
    end component;

    -- Period Jitter (unit interval) for block DCM_INST = 0.17 UI
    -- Period Jitter (Peak-to-Peak) for block DCM_INST = 0.63 ns
    component DCM
    generic( CLK_FEEDBACK : string := "1X";
    CLKDV_DIVIDE : real := 2.0;
    CLKFX_DIVIDE : integer := 1;
    CLKFX_MULTIPLY : integer := 4; ---sonst 4 !!!
    CLKIN_DIVIDE_BY_2 : boolean := FALSE;
    CLKIN_PERIOD : real := 10.0;
    CLKOUT_PHASE_SHIFT : string := "NONE";
    DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
    DFS_FREQUENCY_MODE : string := "LOW";
    DLL_FREQUENCY_MODE : string := "LOW";
    DUTY_CYCLE_CORRECTION : boolean := TRUE;
    FACTORY_JF : bit_vector := x"8080";
    PHASE_SHIFT : integer := 0;
    STARTUP_WAIT : boolean := FALSE;
    DSS_MODE : string := "NONE");
    port ( CLKIN : in std_logic;
    CLKFB : in std_logic;
    RST : in std_logic;
    PSEN : in std_logic;
    PSINCDEC : in std_logic;
    PSCLK : in std_logic;
    DSSEN : in std_logic;
    CLK0 : out std_logic;
    CLK90 : out std_logic;
    CLK180 : out std_logic;
    CLK270 : out std_logic;
    CLKDV : out std_logic;
    CLK2X : out std_logic;
    CLK2X180 : out std_logic;
    CLKFX : out std_logic;
    CLKFX180 : out std_logic;
    STATUS : out std_logic_vector (7 downto 0);
    LOCKED : out std_logic;
    PSDONE : out std_logic);
    end component;

    signal CLKDV_BUF : std_logic;
    signal CLKFB_IN : std_logic;
    signal CLKFX_BUF : std_logic;
    signal CLKFX180_BUF : std_logic;
    signal CLKIN_IBUFG : std_logic;
    signal CLK0_BUF : std_logic;
    signal GND1 : std_logic;

    begin
    GND1 <= '0';
    CLKDV_BUFG_INST : BUFG
    port map (I=>CLKDV_BUF,
    O=>CLKDV_OUT);

    CLKFX_BUFG_INST : BUFG
    port map (I=>CLKFX_BUF,
    O=>CLKFX_OUT);

    CLKFX180_BUFG_INST : BUFG
    port map (I=>CLKFX180_BUF,
    O=>CLKFX180_OUT);

    CLKIN_IBUFG_INST : IBUFG
    port map (I=>CLKIN_IN,
    O=>CLKIN_IBUFG);

    CLK0_BUFG_INST : BUFG
    port map (I=>CLK0_BUF,
    O=>CLKFB_IN);

    DCM_INST : DCM
    generic map( CLK_FEEDBACK => "1X",
    CLKDV_DIVIDE => 2.0,
    CLKFX_DIVIDE => 1,
    CLKFX_MULTIPLY => 4,
    CLKIN_DIVIDE_BY_2 => FALSE,
    CLKIN_PERIOD => 15.1515,
    CLKOUT_PHASE_SHIFT => "NONE",
    DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
    DFS_FREQUENCY_MODE => "HIGH",
    DLL_FREQUENCY_MODE => "LOW",
    DUTY_CYCLE_CORRECTION => TRUE,
    FACTORY_JF => x"8080",
    PHASE_SHIFT => 0,
    STARTUP_WAIT => TRUE)
    port map (CLKFB=>CLKFB_IN,
    CLKIN=>CLKIN_IBUFG,
    DSSEN=>GND1,
    PSCLK=>GND1,
    PSEN=>GND1,
    PSINCDEC=>GND1,
    RST=>'0',
    CLKDV=>CLKDV_BUF,
    CLKFX=>CLKFX_BUF,
    CLKFX180=>CLKFX180_BUF,
    CLK0=>CLK0_BUF,
    CLK2X=>open,
    CLK2X180=>open,
    CLK90=>open,
    CLK180=>open,
    CLK270=>open,
    LOCKED=>open,
    PSDONE=>open,
    STATUS=>open);


    end BEHAVIORAL;

    --STATE_MACHINE-FILE :
    ************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity STATE_MACHINE is
    port(CLKX1 : in std_logic;
    USER_START : in std_logic;
    ADDRESS_CONTROL_FINISH : in std_logic;
    MC_READY : in std_logic;
    BRAM1_EN_toMUX : out std_logic; --Ausgangssignale zu BRAM1
    BRAM1_EN_SEND : out std_logic;
    BRAM1_RESET_toMUX : out std_logic;
    BRAM1_RESET_SEND : out std_logic;
    BRAM2_EN_RECEIVE : out std_logic; --Ausgangssignale zu BRAM2
    BRAM2_EN_toMUX : out std_logic;
    BRAM2_RESET_toMUX : out std_logic;
    BRAM2_WRITE_EN : out std_logic;
    MUX_RESET : out std_logic;
    DES_EN : out std_logic;
    SER_NEN : out std_logic;
    SER_RESET : out std_logic;
    ADDR_CONTROL_RESET_NEN : out
    std_logic;--ADDRESS_CONTROL_RESET_(and)NotENable
    MC_READ : out std_logic;
    LED_Z0 : out std_logic;
    LED_Z2 : out std_logic--;
    );
    end STATE_MACHINE;--Moore-Automat

    architecture Behavioral of STATE_MACHINE is

    type STATES is (Z0, Z1, Z2);
    signal STATE: STATES := Z0;
    signal NEXT_S: STATES := Z0;


    signal STATE_Z0, STATE_Z2 : std_logic;


    begin

    STATE_MEMORY: process(CLKX1)
    begin
    if CLKX1'event and CLKX1 = '1' then--eventuell Flanke ändern?
    STATE <= NEXT_S;
    end if;
    end process;

    DEFINE_NEXT_STATE: process(USER_START, ADDRESS_CONTROL_FINISH, MC_READY
    ,STATE)
    begin
    case STATE is
    when Z0 => if USER_START = '1' then
    NEXT_S <= Z1;
    else
    NEXT_S <=Z0;
    end if;
    when Z1 => if ADDRESS_CONTROL_FINISH = '1' then
    NEXT_S <= Z2;
    else
    NEXT_S <=Z1;
    end if;
    when Z2 => if MC_READY = '1' then
    NEXT_S <= Z0;
    else
    NEXT_S <=Z2;
    end if;
    end case;
    end process;

    SET_OUTPUTS: process(STATE)
    begin
    case STATE is
    when Z0 => BRAM1_EN_toMUX <= '0';
    BRAM1_EN_SEND <= '0';
    BRAM1_RESET_toMUX <= '1';
    BRAM1_RESET_SEND <= '1';
    BRAM2_EN_RECEIVE <= '0';
    BRAM2_EN_toMUX <= '0';
    BRAM2_RESET_toMUX <= '1';
    BRAM2_WRITE_EN <= '0';
    MUX_RESET <= '1';
    DES_EN <= '0';
    SER_NEN <= '1';
    SER_RESET <= '1';
    ADDR_CONTROL_RESET_NEN <= '1';
    MC_READ <= '0';
    when Z1 => BRAM1_EN_toMUX <= '0';
    BRAM1_EN_SEND <= '1';
    BRAM1_RESET_toMUX <= '1';
    BRAM1_RESET_SEND <= '0';
    BRAM2_EN_RECEIVE <= '1';
    BRAM2_EN_toMUX <= '0';
    BRAM2_RESET_toMUX <= '1';
    BRAM2_WRITE_EN <= '1';
    MUX_RESET <= '1';
    DES_EN <= '1';
    SER_NEN <= '0';
    SER_RESET <= '0';
    ADDR_CONTROL_RESET_NEN <= '0';
    MC_READ <= '0';
    when Z2 => BRAM1_EN_toMUX <= '1';
    BRAM1_EN_SEND <= '0';
    BRAM1_RESET_toMUX <= '0';
    BRAM1_RESET_SEND <= '1';--eventuall ändern !
    BRAM2_EN_RECEIVE <= '0';
    BRAM2_EN_toMUX <= '1';
    BRAM2_RESET_toMUX <= '0';
    BRAM2_WRITE_EN <= '0';
    MUX_RESET <= '0';
    DES_EN <= '0';
    SER_NEN <= '1';
    SER_RESET <= '1';
    ADDR_CONTROL_RESET_NEN <= '1';
    MC_READ <= '1';
    end case;
    end process;

    INDICATE_STATE: process(STATE)
    begin
    case STATE is
    when Z0 => STATE_Z0 <= '1';
    STATE_Z2 <= '0';
    when Z1 => STATE_Z0 <= '0';
    STATE_Z2 <= '0';
    when Z2 => STATE_Z0 <= '0';
    STATE_Z2 <= '1';
    end case;
    end process;


    LED_Z0 <= STATE_Z0; --die LEDs signalisieren den aktuellen Zustand
    LED_Z2 <= STATE_Z2;

    end Behavioral;

    ADDRESS_CONTROL-FILE :
    ********************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;


    entity ADDRESS_CONTROL is
    generic(
    ADDRESS_WIDTH : positive := 10
    );
    Port ( CLKX1 : in std_logic;
    RESET_NEN : in STD_LOGIC;
    ADDR_BRAM1 : out STD_LOGIC_VECTOR (ADDRESS_WIDTH-1 downto
    0);
    ADDR_BRAM2 : out STD_LOGIC_VECTOR (ADDRESS_WIDTH-1 downto
    0);
    FINISH : out std_logic
    );
    end ADDRESS_CONTROL;

    architecture Behavioral of ADDRESS_CONTROL is

    signal FINISH_FLAG : std_logic;
    signal CNT : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
    constant MAX_ADDRESS : std_logic_vector(ADDRESS_WIDTH-1 downto 0) :=
    "1111111111";

    begin

    CHANGE_ADDRESS: process(CLKX1)
    begin
    if CLKX1'event and CLKX1 = '1' then
    if RESET_NEN = '1' then
    CNT <= (others => '0');
    FINISH_FLAG <= '0';
    else
    if CNT = MAX_ADDRESS then
    FINISH_FLAG <= '1';
    else
    CNT <= CNT + 1;
    FINISH_FLAG <= '0';
    end if;
    end if;
    end if;
    end process;

    ADDR_BRAM1 <= CNT;
    ADDR_BRAM2 <= CNT;

    FINISH <= FINISH_FLAG;

    end Behavioral;

    --SER-FILE :
    ****************************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity SER16to1 is
    Port ( CLKX8 : in std_logic; --8facher Takt (bezogen auf den Takt des
    16 Bit breiten Datenbus)
    CLKX8_180 : in std_logic; --8facher Takt invertiert
    RESET : in std_logic; --Reseteingang
    NotENABLE : in std_logic;
    DATA_PARALLEL : in std_logic_vector(15 downto 0);
    ODATA_LVDSP : out std_logic;
    ODATA_LVDSN : out std_logic);
    end SER16to1;

    architecture Behavioral of SER16to1 is

    signal DATA_POS_EDGE, DATA_NEG_EDGE, DOUBLE_R_DATA : std_logic;
    signal CNT, CNT0: std_logic_vector(2 downto 0):= (others => '0');

    begin

    OFDDRRSE_inst : FDDRRSE --double datarate
    port map (
    Q => DOUBLE_R_DATA, -- Data output (connect directly to
    top-level port)
    C0 => CLKX8, -- 0 degree clock input
    C1 => CLKX8_180, -- 180 degree clock input
    --Commonly, the Digital Clock Manager
    --(DCM) generates the two clock signals by mirroring an
    --incoming signal, then shifting it 180 degrees. This approach
    --ensures minimal skew between the two signals.
    CE => '1', -- Clock enable input
    D0 => DATA_POS_EDGE, -- Posedge data input
    D1 => DATA_NEG_EDGE, -- Negedge data input
    R => NotENABLE, -- Synchronous reset input
    S => '0' -- Synchronous preset input
    );

    OBUFDS_inst : OBUFDS --LVDS-Output
    generic map(
    IOSTANDARD => "LVDSEXT_25")--Standard: siehe Datasheet S.62(Tabelle
    36)
    port map (
    O => ODATA_LVDSP, -- Diff_p output (connect directly to
    top-level port)
    OB => ODATA_LVDSN, -- Diff_n output (connect directly to
    top-level port)
    I => DOUBLE_R_DATA -- Buffer input
    );

    --***********************************************************************
    -- Prozess: COUNT
    --
    --Der Prozess fungiert als taktsynchroner Zähler von 0 bis 7 mit
    --synchronem Reseteingang(highaktiv), der den Zählerstand auf Null
    setzt.
    --
    -- Input (->): CLK8X, RESET
    --***********************************************************************
    COUNT: process(CLKX8_180)
    begin
    if(CLKX8_180'event and CLKX8_180='1') then
    if RESET = '1' then
    CNT <= (others => '0');
    CNT0 <= (others => '0');
    else
    CNT <= CNT + '1';
    CNT0 <= CNT;
    end if;
    end if;
    end process;


    --***********************************************************************
    -- Prozess: MULTIPLEX
    --
    --Der Prozess legt in Abhängigkeit des Zählerstandes in CNT zwei
    --aufeinanderfolgende Bits des parallelen Datenbusses DATA_PARALLEL an
    --DATA_POS_EDGE und DATA_NEG_EDGE an.
    --
    -- Input (->): CLK8X_180, DATA_PARALLEL, CNT
    -- Output(<-): DATA_POS_EDGE, DATA_NEG_EDGE
    --***********************************************************************
    MULTIPLEX: process(CLKX8_180)
    begin
    if(CLKX8_180'event and CLKX8_180='1') then
    if(CNT0 = 0) then
    DATA_POS_EDGE <= DATA_PARALLEL(0);--eventuell Reihenfolge aus
    SERDES-File verwenden
    DATA_NEG_EDGE <= DATA_PARALLEL(1);
    elsif(CNT0 = 1) then
    DATA_POS_EDGE <= DATA_PARALLEL(2);
    DATA_NEG_EDGE <= DATA_PARALLEL(3);
    elsif(CNT0 = 2) then
    DATA_POS_EDGE <= DATA_PARALLEL(4);
    DATA_NEG_EDGE <= DATA_PARALLEL(5);
    elsif(CNT0 = 3) then
    DATA_POS_EDGE <= DATA_PARALLEL(6);
    DATA_NEG_EDGE <= DATA_PARALLEL(7);
    elsif(CNT0 = 4) then
    DATA_POS_EDGE <= DATA_PARALLEL(8);
    DATA_NEG_EDGE <= DATA_PARALLEL(9);
    elsif(CNT0 = 5) then
    DATA_POS_EDGE <= DATA_PARALLEL(10);
    DATA_NEG_EDGE <= DATA_PARALLEL(11);
    elsif(CNT0 = 6) then
    DATA_POS_EDGE <= DATA_PARALLEL(12);
    DATA_NEG_EDGE <= DATA_PARALLEL(13);
    else
    DATA_POS_EDGE <= DATA_PARALLEL(14);
    DATA_NEG_EDGE <= DATA_PARALLEL(15);
    end if;
    end if;
    end process;--nach dem Reset wird die seriellen Daten mit CLK8X/2
    verzögert ausgegeben


    end Behavioral;


    --DES-FILE :
    ****************************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    -- Die Daten werden nach 2 Perioden von CLKX1 an DATA_OUT ausgegeben
    library UNISIM;
    use UNISIM.VComponents.all;

    entity DES1to16 is
    Port ( ENABLE : in std_logic; --mit DCM_LOCKED verbinden
    IDATA_LVDSP : in std_logic;
    IDATA_LVDSN : in std_logic;
    CLKX8 : in STD_LOGIC;
    CLKX8_180 : in STD_LOGIC;
    CLKX1 : in STD_LOGIC;
    DATA_OUT : out STD_LOGIC_VECTOR (15 downto 0));
    end DES1to16;

    architecture Behavioral of DES1to16 is

    signal DOUBLE_RATE_DATA_DES, DATA_NEG_EDGE, DATA_POS_EDGE : std_logic;
    signal DD2 : std_logic_vector(15 downto 0);
    signal DD1 : std_logic_vector(13 downto 0);

    begin

    IBUFDS_inst : IBUFDS
    generic map (
    IOSTANDARD => "LVDSEXT_25")
    port map (
    O => DOUBLE_RATE_DATA_DES, -- Clock buffer output
    I => IDATA_LVDSP, -- Diff_p clock buffer input (connect directly
    to top-level port)
    IB => IDATA_LVDSN -- Diff_n clock buffer input (connect directly
    to top-level port)
    );

    double_data_rate1: process(CLKX8)
    begin
    if CLKX8'event and CLKX8 = '1' then
    DATA_POS_EDGE <= DOUBLE_RATE_DATA_DES;
    end if;
    end process;

    double_data_rate2: process(CLKX8_180)
    begin
    if CLKX8_180'event and CLKX8_180 = '1' then
    DATA_NEG_EDGE <= DOUBLE_RATE_DATA_DES;
    end if;
    end process;

    process(CLKX8_180) begin
    if(CLKX8_180'event and CLKX8_180='1') then
    DD2(15) <= DATA_POS_EDGE;
    DD2(14) <= DATA_NEG_EDGE;
    DD2(13) <= DD2(15);
    DD2(12) <= DD2(14);
    DD2(11) <= DD2(13);
    DD2(10) <= DD2(12);
    DD2(9) <= DD2(11);
    DD2(8) <= DD2(10);
    DD2(7) <= DD2(9);
    DD2(6) <= DD2(8);
    DD2(5) <= DD2(7);
    DD2(4) <= DD2(6);
    DD2(3) <= DD2(5);
    DD2(2) <= DD2(4);
    DD2(1) <= DD2(3);
    DD2(0) <= DD2(2);
    end if;
    end process;

    process(CLKX1) begin
    if(CLKX1'event and CLKX1 = '1') then
    DD1 <= DD2(15 downto 2);
    end if;
    end process;

    process(CLKX1) begin
    if(CLKX1'event and CLKX1 = '1') then
    if ENABLE = '1' then
    DATA_OUT <= DD2(1 downto 0) & DD1;
    else
    DATA_OUT <= (others => '0');
    end if;
    end if;
    end process;


    end Behavioral;


    --MUX-FILE :
    ****************************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity MUX is
    generic(
    DATA_WIDTH: positive := 4;--Breite des Datenbusses
    ADRESS_WIDTH_toMC: positive := 12;
    CONTROL_WIDTH: positive := 2--Anzahl der Steuerleitungen
    );
    Port ( DATA1 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);--Daten
    von BRAM1
    DATA2 : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);--Daten
    von BRAM2
    DATA_OUT : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto
    0);--Datenbus zum Mikrocontroller
    ADRESS1 : out std_logic_vector(ADRESS_WIDTH_toMC-1 downto
    0);--Adressbusse zu den BRAMs
    ADRESS2 : out std_logic_vector(ADRESS_WIDTH_toMC-1 downto 0);
    RESET : in std_logic;--asynchrones Resetsignal von der
    State-Machine
    INDICATION : out STD_LOGIC_VECTOR(CONTROL_WIDTH-1 downto
    0);--Kontrollbus zum Mikrocontroller
    CLK_extMC : in STD_LOGIC;--Auslesetakt für die BRAMs (vom
    Mikrocontroller generiert)
    CLK_fromMC :eek:ut STD_LOGIC
    );
    end MUX;

    architecture Behavioral of MUX is


    signal CHOOSE: std_logic := '0';
    signal ADRESS : std_logic_vector(ADRESS_WIDTH_toMC-1 downto 0);
    signal CLK_MC : std_logic;
    signal DATA_OUTs : std_logic_vector(DATA_WIDTH-1 downto 0);
    constant MAX_ADRESS : std_logic_vector(ADRESS_WIDTH_toMC-1 downto 0) :=
    "111111111111";--:= (others => '1');

    begin

    IBUFG_inst : IBUFG
    generic map (
    IOSTANDARD => "LVTTL")--Vmax = 3,3 V
    port map (
    O => CLK_MC, -- Clock buffer output
    I => CLK_extMC -- Clock buffer input (connect directly to
    top-level port)
    );


    COUNT: process(RESET,CLK_MC)
    begin
    if RESET = '1' then
    ADRESS <= (others => '0'); --eventuell auf 2 oder 3 setzen
    (Verzögerung des DES)
    INDICATION <= "00";
    CHOOSE <= '0';
    DATA_OUTs <= "0000";
    elsif CLK_MC'event and CLK_MC = '1' then
    if ADRESS = MAX_ADRESS and CHOOSE = '1' then
    INDICATION <= "11";

    elsif CHOOSE = '1' then
    INDICATION <= "10";
    ADRESS <= ADRESS + 1;
    DATA_OUTs <= DATA2;

    CHOOSE <= not CHOOSE;
    elsif CHOOSE = '0' then
    INDICATION <= "01";
    DATA_OUTs <= DATA1;

    CHOOSE <= not CHOOSE;
    end if;
    end if;
    end process;

    ADRESS1 <= ADRESS;
    ADRESS2 <= ADRESS;

    DATA_OUT <= DATA_OUTs;

    CLK_fromMC <= CLK_MC;


    end Behavioral;


    --BRAM_SEND-FILE :
    *****************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity BRAM_SEND is
    port(
    DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
    Data Output
    DATA_toSER : out std_logic_vector(15 downto 0); -- Port B
    16-bit Data Output
    ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
    Address Input
    ADDRESS_SEND: in std_logic_vector(9 downto 0); -- Port B 10-bit
    Address Input
    CLK_MUX : in std_logic; -- Port A Clock
    CLKX1 : in std_logic; -- Port B Clock
    EN_toMUX : in std_logic; -- Port A RAM Enable Input
    EN_SEND : in std_logic; -- PortB RAM Enable Input
    RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
    Input
    RESET_SEND : in std_logic -- Port B Synchronous Set/Reset Input
    );
    end BRAM_SEND;

    architecture Behavioral of BRAM_SEND is

    begin

    RAMB16_S4_S18_instBRAM_S : RAMB16_S4_S18
    generic map (
    INIT_A => X"0", -- Value of output RAM registers on Port A at
    startup
    INIT_B => "000000000000000000", -- Value of output RAM registers
    on Port B at startup
    SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
    SRVAL_B => "000000000000000000", -- Port B ouput value upon SSR
    assertion
    WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
    NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
    NO_CHANGE
    SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING",
    "GENERATE_X_ONLY", "ALL
    -- The following INIT_xx declarations specify the initial
    contents of the RAM
    -- Port A Address 0 to 1023, Port B Address 0 to 255
    INIT_00 =>
    X"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa",
    INIT_01 =>
    X"31A24DB059A566389894651BBD99BD2D8C9B354390CB86B5E70923CC10B65204",
    INIT_02 =>
    X"B75A641ACB7C72335E48B321BA380BC5AE9283A6251BEA66393419843808728D",
    INIT_03 =>
    X"3D2602D4EB565E4BD3ED9E420A33DC4880330B8BE847CCD78EA28B0D1629203B",
    INIT_04 =>
    X"7B584C96B3261E267E525534B3690D7A2AD1CC72E9BEB9DC5AE412A0D3E34174",
    INIT_05 =>
    X"4764D5C1BA875991B1B88A0DC825861D6714624105DBEEC93E9559134288753B",
    INIT_06 =>
    X"2A24E99ECED52732D58D25C5872420D4D2B6DC080B272BEA253E5AA815B2AA5E",
    INIT_07 =>
    X"A9EAB4871BD31ED9E7ACA6A2A562D3997107CE0748D5273B21A54A715116623A",
    INIT_08 =>
    X"0E8D512E0DDDA220348A7EC887150339A019A1CADA6B6C67C646B272C65B3945",
    INIT_09 =>
    X"47658CE4977E28C8BA23A832911095B56EAD0D46DE2E6D6A23B0D6A022B798C8",
    INIT_0A =>
    X"6D5D528AC725EB0D5AC9AA396A985E2041340DCCE61726EA3E62AD8796790D74",
    INIT_0B =>
    X"A63A2C98BD68A190ECE31E3705A9378C9D1E8552B3E7E5EE00A8D013C727A363",
    INIT_0C =>
    X"825E50D3C337E391D285B3E810E3A0D7685653D94D3E71908B1A0B41E592532B",
    INIT_0D =>
    X"37BBD94017A3516B4967BD75065601C1A07433BCD239DE86D92D4DA53D55B981",
    INIT_0E =>
    X"3E764373E02864893E1301E208892D2569D1ED0979D06EC0000928245A49AA11",
    INIT_0F =>
    X"AEA8387C19D3BAD3DED01AE68780851E039D6569CD94656616126E516764E078",
    INIT_10 =>
    X"9107D66D37276715944658B74A886219E8245299D83648117887622ACD2C35C5",
    INIT_11 =>
    X"397370A02C1787D6B595D4A5AC755CBE31E689D3051A08405ECC1E99030855C1",
    INIT_12 =>
    X"7331991EA02E2DEA3D652D24661C90E9D16940AA1AAE91399003462DD631AC94",
    INIT_13 =>
    X"A2CB044E7A59C17279009084672932CC3533E4EBED516AC7721ECBD266883CD1",
    INIT_14 =>
    X"A1765046C93423316DD2B122D28AD0DCDD103BA92EE602D8422012220C91032D",
    INIT_15 =>
    X"4592C5C36758B8D5D1C023E6382A362A9D368B2D4A55B635A832D51AA42728CE",
    INIT_16 =>
    X"EE8C72A89284A695C3D69DB5902E5319A2EA837D7609ACA4AA6CA489B7D302B1",
    INIT_17 =>
    X"5C3E3E9E9C0878C8AC6ECBE615836CCB43C1A5E4603224A7B01C4D30BA613848",
    INIT_18 =>
    X"70CE6A81349A33784ED013CDB6E62C469B471315970CB17B7589025586833A6C",
    INIT_19 =>
    X"05540E35E27C1277A11C0E6D17D114926B534032D816C57B7B11B524306498ED",
    INIT_1A =>
    X"708D82706D0B19581D1A8E58BCE5D5296C61CA6022E55BDD1DD16162094D4EED",
    INIT_1B =>
    X"2A693B87804ABE0A13AA3AB724B2A791C18DA76921DC35228D5EC1D9763C6725",
    INIT_1C =>
    X"D990AB41C6BD350363DB64D013484D6A59A0065A6DE67C00A7A256C28001D80B",
    INIT_1D =>
    X"E820A2025B1818A1A471AC876C288829A0594A85445B1B7834C73D5434DEC9E5",
    INIT_1E =>
    X"5247B680E5856510890DEB25C1835930256A2CEE12857D397DDE185EB277186D",
    INIT_1F =>
    X"BA60A017C650389739C753904943A841538E0670A65E83AC4043790C30E6669A",
    INIT_20 =>
    X"246C9E9DCB5D2D4CC66AA13C65AC49401B640926975ED881D5BE04838EA68123",
    INIT_21 =>
    X"3B98B3398E27C17667801A7AB02CA95E8756A83B02A24CD777936336AB82B0B7",
    INIT_22 =>
    X"EAB1A46DD0A426D85C40E307D858ADC1608B8CCDECD0CDC508129ED37712EA08",
    INIT_23 =>
    X"906539C37E94749A9EE3587351CB4DD87E382834ACABCB5C1B805D840C3C22A0",
    INIT_24 =>
    X"23BBD272324592E18081970242A3BA026693A37DA93CD1AC2CB3A7A8186951B5",
    INIT_25 =>
    X"BA4CD0D6ABC1C9948551DAA39CDA85BE7D666853B026573D5A6149D83C83230B",
    INIT_26 =>
    X"E82DE897419589BE836419AC18918889C2D9A1EACDE94ABD93E92A845B9D6C00",
    INIT_27 =>
    X"6061B4CDA55B0B32779A270D19D8AA0531A0C89BA1E17A4016A002ADD2235777",
    INIT_28 =>
    X"9CB86AED9549A707235322D3C5463796DE311DC541AB2CD0912CDE44B8DDCE71",
    INIT_29 =>
    X"B43024155B29AC819D78944DA8574EED8A0E357072CEE0916AE57D686471EE3C",
    INIT_2A =>
    X"DD6C8048AE468CD92990C481D7C1EB6ED8681E022A608828D190B171463592C4",
    INIT_2B =>
    X"11ED653750DC76D8B653769DE776DCA4279A0DC428ABBE7934917B70EB280301",
    INIT_2C =>
    X"E679CCAB8C41DA9B3C68E037E62CCDA28AC3B962EAB29EB840A2A6648C910749",
    INIT_2D =>
    X"B3E18D758E9B71D12B73BB60DEB04C7951BC8D98BD468207AC1C06C1C04DB702",
    INIT_2E =>
    X"B2A81000A55C3B44BE30D942E9E6068DA8BE420998BE13EB6813059B03C71897",
    INIT_2F =>
    X"CD935A639274D03D83B1597E77BA72725D6543414079037792295D6D3ED02B6E",
    INIT_30 =>
    X"D3EB4528A277C02A53B405BAC8C291B90D86A83AAB0C0659A64D9A1722B2E7D6",
    INIT_31 =>
    X"A52B397960E0BB813D650DEDDE8934E6E7CC0CD738835C83BD0670310A89035E",
    INIT_32 =>
    X"3008A539DA3B2B0CC660AB7C3335BD7B4E7851EDBB1D82494D09EC22011E5C59",
    INIT_33 =>
    X"867370158A154636585837376EB91D7B5A3CA037846706665D94A89DC25E6590",
    INIT_34 =>
    X"52B23273DD410DD802E4D86211B4866A46D719B12187B7C9E21DC9D816CA43A9",
    INIT_35 =>
    X"494494A876798145C8D4C19D2C4828D2698C994356323A4A3444ED9D03D67DD9",
    INIT_36 =>
    X"3560BB813222D28614B06885C11BADB5481ADE0402EE672076DD96935A02EBAC",
    INIT_37 =>
    X"747673B5ACB7B60DC6B8BA3B99612D36B82D479503719C6C0BBE9E9BB0AB5C50",
    INIT_38 =>
    X"7E5B3037525C8044D085A4C294204C32786478A4D7D08D1C2E91486C5CCA00DA",
    INIT_39 =>
    X"72E9D33644047E9C975DC8EACD22A7C1BCA17E08AC475B5382D57712DD5B9495",
    INIT_3A =>
    X"E1ECEA16C38C7B91004A1DB9621DEBE7AAAA53319860BAB59736958915AE8110",
    INIT_3B =>
    X"06D6C17D9EA65C31707CE127460640BE179626E758C41A5D117E85748E79770D",
    INIT_3C =>
    X"46746B699DBE74D2582A669821825634984163E8C49B48494A71122A135CA2EC",
    INIT_3D =>
    X"E63E9317D9678103A976196BE59BB75816A6140C68E95221567E103CB184E5A1",
    INIT_3E =>
    X"55BADDCBB01705A7A516A9EE5261952711D56002138E300DC5A8068ACE48243E",
    INIT_3F =>
    X"DA2A16DDDC46264E61237022D97510AA6AC244EA0A66C6D62A0A934EDB27C9CB",
    -- The next set of INITP_xx are for the parity bits
    -- Port A Address 0 to 1023, Port B Address 0 to 255
    INITP_00 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    INITP_01 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    -- Port A Address 1024 to 2047, Port B Address 256 to 511
    INITP_02 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    INITP_03 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    -- Port A Address 2048 to 3071, Port B Address 512 to 767
    INITP_04 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    INITP_05 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    -- Port A Address 3072 to 4095, Port B Address 768 to 1023
    INITP_06 =>
    X"0000000000000000000000000000000000000000000000000000000000000000",
    INITP_07 =>
    X"0000000000000000000000000000000000000000000000000000000000000000")
    port map (
    DOA => DATA_toMUX, -- Port A 4-bit Data Output
    DOB => DATA_toSER, -- Port B 16-bit Data Output
    DOPB => open, -- Port B 2-bit Parity Output
    ADDRA => ADDRESS_MUX, -- Port A 12-bit Address Input
    ADDRB => ADDRESS_SEND, -- Port B 10-bit Address Input
    CLKA => CLK_MUX, -- Port A Clock
    CLKB => CLKX1, -- Port B Clock
    DIA => "1111", -- Port A 4-bit Data Input
    DIB => "1111111111111111", -- Port B 16-bit Data Input
    DIPB => "11", -- Port-B 2-bit parity Input
    ENA => EN_toMUX, -- Port A RAM Enable Input
    ENB => EN_SEND, -- PortB RAM Enable Input
    SSRA => RESET_toMUX, -- Port A Synchronous Set/Reset Input
    SSRB => RESET_SEND, -- Port B Synchronous Set/Reset Input
    WEA => '0', -- Port A Write Enable Input
    WEB => '0' -- Port B Write Enable Input
    );


    end Behavioral;


    --BRAM_RECEIVE-FILE :
    *************************************************************************************

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    library UNISIM;
    use UNISIM.VComponents.all;

    entity BRAM_RECEIVE is
    port(
    DATA_toMUX : out std_logic_vector(3 downto 0); -- Port A 4-bit
    Data Output
    DATA_fromDES : in std_logic_vector(15 downto 0); -- Port B
    16-bit Data Intput
    ADDRESS_MUX: in std_logic_vector(11 downto 0); -- Port A 12-bit
    Address Input
    ADDRESS_RECEIVE: in std_logic_vector(9 downto 0); -- Port B
    10-bit Address Input
    CLK_MUX : in std_logic; -- Port A Clock
    CLKX1_PS : in std_logic; -- Port B Clock (PS: phase-shifted)
    Verzögerung des DUTs
    EN_toMUX : in std_logic; -- Port A RAM Enable Input
    EN_RECEIVE : in std_logic; -- PortB RAM Enable Input
    RESET_toMUX : in std_logic; -- Port A Synchronous Set/Reset
    Input
    WRITE_ENABLE : in std_logic
    );
    end BRAM_RECEIVE;

    architecture Behavioral of BRAM_RECEIVE is

    begin

    RAMB16_S4_S18_instBRAM_R : RAMB16_S4_S18
    generic map (
    INIT_A => X"0", -- Value of output RAM registers on Port A at
    startup
    INIT_B => "000000000000000000", -- Value of output RAM registers
    on Port B at startup
    SRVAL_A => X"0", -- Port A ouput value upon SSR assertion
    SRVAL_B => "000000000000000000", -- Port B ouput value upon SSR
    assertion
    WRITE_MODE_A => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
    NO_CHANGE
    WRITE_MODE_B => "WRITE_FIRST", -- WRITE_FIRST, READ_FIRST or
    NO_CHANGE
    SIM_COLLISION_CHECK => "ALL", -- "NONE", "WARNING",
    "GENERATE_X_ONLY", "ALL
    -- The following INIT_xx declarations specify the initial
    contents of the RAM
    -- Port A Address 0 to 1023, Port B Address 0 to 255
    INIT_00 =>
    X"0B3590A1A174768987DBEA2C0A79BC3074933CE64B47E2B94839CABE379ECC71",
    INIT_01 =>
    X"757BD429738DA3B5A0B9494ED34701908332C6C3E6E7B76EA71E874BD75ACC6D",
    INIT_02 =>
    X"EE5D23172975488DE0E4C2CBB8107AC1E5944BB3DA3C0EB51318D2EA77138A60",
    INIT_03 =>
    X"579DB42A34470D66B69964892EE560544E7403D0487D9CA8010837BDAD631005",
    INIT_04 =>
    X"2399A631B2036C2EB2AC8E53ABE27DEDBC5188D14B3A3392557ABE3738321422",
    INIT_05 =>
    X"C8090DEA9B8B3E883E6489635B31E416468ED9687A5B358874275327AE030008",
    INIT_06 =>
    X"731B6C3308B38B6C0D326BB6D3E06770238588261AA155D9C1C4A5A3D13429C7",
    INIT_07 =>
    X"C918863BBECA868E6B3C85928E1CBDB6C38E6CA474D1679D512EC630D4714340",
    INIT_08 =>
    X"10566A52029BCCB3908DEDE5BCD66D8A0B9A8EA8209E86E46846C0B2809843B9",
    INIT_09 =>
    X"859E4E4D966313D79E3D6468BE556E5D2E86E7DED1E6BCA47B8A969969AB0356",
    INIT_0A =>
    X"5C8D1CEBB5E6E922785C707BED2633EB00BD915C902A056B5D06ED024914310A",
    INIT_0B =>
    X"550D1E5B4D9A10859202097C13533CDD9A9760BDB0D15C5A8404AC334CE35E32",
    INIT_0C =>
    X"134CB61CC92880A2A3A07045E587DECE9B9211B70944E4A2521E0940AC9113E3",
    INIT_0D =>
    X"EC82D7253C621B02A01DB21467D4A940EAE7491CE779070CDD17C0180DA6E7D6",
    INIT_0E =>
    X"7515EB022A8849ACA9A5C75251862103763144ADDB5AD12D599A57A120E4223B",
    INIT_0F =>
    X"24A096D40000CCBC1AAB8A64746725837098DE73BDBDC5324B670B7E29240533",
    INIT_10 =>
    X"D53CE81960775D439C74ED1D2754229BD42D46DDB9950CE2859B7B8241166535",
    INIT_11 =>
    X"A7A790B1BED30631AB5EC5B9BDB59EAB0CAC4E3D88EDDD6A1D182AADA54B3D4A",
    INIT_12 =>
    X"251CBA57185B5D4668AB34A466D81970AD1CEBE3AC0A187E3EB74187A6AC2CDA",
    INIT_13 =>
    X"7EEDE77DD75437D53E9207A92BBC67914A41A408566072127EA3B2DEB9D53C06",
    INIT_14 =>
    X"E0D1C599386389B6B54BA14C2B789E3A979811CB416933A62937ADD04EB189AB",
    INIT_15 =>
    X"464662DA8020A74474A87C2A52A407C41CE69291558C3937C34C86DACA5D2775",
    INIT_16 =>
    X"16A4643C5E97803607E2864BE61C5BA3014B497CE6128D18A6E77C582681A4A8",
    INIT_17 =>
    X"C6A37A99254E0DD0462D39BEC8034DCECCDAE6BB732134CD59878443E675A089",
    INIT_18 =>
    X"739914A602CD098E674EE2A54AD370EC953A4ADCB8D35EA090394325DC72B3CC",
    INIT_19 =>
    X"63A805EACD00E597D70C8AB5A681BA8294272390BE1C33BC6D1725509C23EDAC",
    INIT_1A =>
    X"B144B8C3B9B62748CE689E60B1C5A36DCE9E268D484B9154976ADAE407567E18",
    INIT_1B =>
    X"D4077889214A840C1A88E3CADE1A880EC65E97784521D515C37D575B0ABEA0E1",
    INIT_1C =>
    X"41403DE8985618E4D9D71A8856371D92C76DBA6E890929A021DCBA19051A60C4",
    INIT_1D =>
    X"6DACB5AA04550902A834C0B4031A04A6BC0DB5149DCA4BB2B9C7EE058586885C",
    INIT_1E =>
    X"DD3DE0AB96E7EED41168A0EA91E9D0715A48DA1C947D0383DD73A5BBECE04E38",
    INIT_1F =>
    X"6864B20C2D189816EC938CB71656978122D7781DA562ADB21CAED81AC5E2A53A",
    INIT_20 =>
    X"B2236BB14A6770370DED633D27ECB88C50622A3D7D77EB87A7E0379662DBCA98",
    INIT_21 =>
    X"289EC1D363D15E3B38601D02A13523815674B6B59335BB8815309DA65EC8381B",
    INIT_22 =>
    X"3EBAE3DE211C45498C23112D6765593CE3B6CE3C436C2D16A8E84BD7D4968C8B",
    INIT_23 =>
    X"DC91077562070CDC3DB6CECE4776AD272663D3467C2C162C06041C9017714181",
    INIT_24 =>
    X"2E1715E9C1C88E9A1D23B47E7EB3CA8C1D71DB28E4A5AE90D3E6A8D4D22D34E3",
    INIT_25 =>
    X"62C6327D4A632400B881AC5C789708D4434B51E6A006C582B3201913B742A06C",
    INIT_26 =>
    X"34BB8C76C978EC4BB4092BD8645E5B7B7BA4465D0D7038ADE925D8C17133E249",
    INIT_27 =>
    X"02E14B2469EA143810931358BBE92B3917948E026B91B8207BBD18CCB41B0536",
    INIT_28 =>
    X"B15BDDB22ED3989D6A58D0A63D1D1CEBDB8340E917447B31950EC8C347BB0D17",
    INIT_29 =>
    X"66052893E55DC45710706D8E3CBBD618CA2D67162DE6E8EE0AD2049BA2B46777",
    INIT_2A =>
    X"977285925069B73AC154A8ECE130AD752A897E48AC719623504164B83C76E0C5",
    INIT_2B =>
    X"89B4BE42541A847B0223922554D451094A635DE9544205622B36D293799B11A1",
    INIT_2C =>
    X"79B9CD247A7973EA5B762E132C955D0901C3AE80C74CB38CC58C8EBDD4DBE0E3",
    INIT_2D =>
    X"2C92774BAA711678215E1A62B54395664089B050AC764D18463D6E025888103D",
    INIT_2E =>
    X"A94C2C9C964974C62ADC092CC62AA01B53814B569290A0DE47C61E084D49BEDC",
    INIT_2F =>
    X"7BCBA95019C7D167B6A6BC80584578582C9389EE1757C4D506249C2BBAD9BE9C",
    INIT_30 =>
    X"81211DC8374AD2D8AAAE52068C386219D13749970D68D60B97CE1ED587786C32",
    INIT_31 =>
    X"CE616EA9658D4B3724958B4DCB9C7C308929AC8BA7C7B048BE8DD12D31E09A57",
    INIT_32 =>
    X"CAE0555E5C4AED028CE36ECE5CAEA51E5C790CD086D69513970B538117ED91D4",
    INIT_33 =>
    X"79EE0487DC6BC15325DE54501B4E6A86C36291590CAAC1D2300BB75E382066E0",
    INIT_34 =>
    X"48CC0E891D2146B3A1524249B64321EA29EA7A0ECB60066E7AA0CE99035A2B53",
    INIT_35 =>
    X"ACA96E9CDDDEB7CBE385827B481BC8454A6D97117CBAA7E64421E5D9E6C24946",
    INIT_36 =>
    X"4CC35D2066B48B1545E9393DC665EDC8EA458C9753EC40910935507B6A3C8582",
    INIT_37 =>
    X"5C0279A105462789E9AC29566D527E65324A26ECC674D31A3E8A7CED5ACD525D",
    INIT_38 =>
    X"888551B655EC6E6930C940B71B755A7E3EEC888729349B981ECEE2C4A9437681",
    INIT_39 =>
    X"A13539E0D35A409D50E07EACE4D86067D219A133EEA04CBBB8533356EAD153AC",
    INIT_3A =>
    X"D7AE7AA282818050A618B3321458D9190A9C8274402C18C7ED2901487E7D36B0",
    INIT_3B =>
    X"05B4E9256519A36309D976C500ADE14590D51A175C3D6B68351424C15A8462C5",
    INIT_3C =>
    X"9BB38E3071EE97A40156A5AD5DBE49E757E16D1BD195DEC7C7A7D79D488AB5AA",
    INIT_3D =>
    X"13539E09B9339078A1151363907AA370AB6A49B1366A6889DCD2AD14741DA981",
    INIT_3E =>
    X"765B0AED38804B7D11A8CC166E97A3A3676AE7A1C656A80116A394203D03D4B8",
    INIT_3F =>
    X"35061DB65D374DB727B6AA34C3ADA0E8D6A4A00489978B220AD0214A73C5D8E9")
    port map (
    DOA => DATA_toMUX, -- Port A 4-bit Data Output
    DOB => open, -- Port B 16-bit Data Output
    DOPB => open, -- Port B 2-bit Parity Output
    ADDRA => ADDRESS_MUX, -- Port A 12-bit Address Input
    ADDRB => ADDRESS_RECEIVE, -- Port B 10-bit Address Input
    CLKA => CLK_MUX, -- Port A Clock
    CLKB => CLKX1_PS, -- Port B Clock
    DIA => "1111", -- Port A 4-bit Data Input
    DIB => DATA_fromDES, -- Port B 16-bit Data Input
    DIPB => "11", -- Port-B 2-bit parity Input
    ENA => EN_toMUX, -- Port A RAM Enable Input
    ENB => EN_RECEIVE, -- PortB RAM Enable Input
    SSRA => RESET_toMUX, -- Port A Synchronous Set/Reset Input
    SSRB => '0', -- Port B Synchronous Set/Reset Input
    WEA => '0', -- Port A Write Enable Input
    WEB => WRITE_ENABLE -- Port B Write Enable Input
    );


    end Behavioral;
     
    Benjamin Todd, Dec 19, 2006
    #2
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