Unsigned Addition

Discussion in 'VHDL' started by Pings, Jul 16, 2010.

  1. Pings

    Pings

    Joined:
    Jul 16, 2010
    Messages:
    1
    Hi,

    I am new to Vhdl and trying to add two usigned numbers. Can anyone help me with it.

    Pings.
    Pings, Jul 16, 2010
    #1
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  2. Pings

    joris

    Joined:
    Jan 29, 2009
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    The Numeric_STD library defines an 'unsigned' type and overloaded '+' operator.

    What is your starting point like?
    joris, Jul 16, 2010
    #2
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