UNSIGNED and sign exteension

A

andy

Hi there

I have defined

signal xx std_logic_vector(2 downto 0);
signal zz unsigned(4 downto 0);

and I want to assign

zz <= unsigned(xx);

without getting an array type mismatch and without doing

zz <= unsigned ("00" & xx);

which works fine but is not very portable and flexible.

Is there a way to 'extend' xx with a ieee library function?

maybe it is trivial, but I cannot get rid of that I am so tired, it is
so late now in Italy now ...

Thanks to who'll reply
 
F

Fidodido

Try

libray ieee;
use ieee.std_logic_arith.all;

....

zz <= conv_unsigned(xx,zz'length);
 

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