Unsigned multiplier

Discussion in 'VHDL' started by Ndf, Oct 2, 2006.

  1. Ndf

    Ndf Guest

    Hello,

    Thanks to Leon de Boer I found this serial 8x8 bit multiplier:
    http://groups.google.fr/group/comp....l multiplier 16&rnum=3&hl=fr#a65c3688017d3710



    Someone can show me how to transform this unsigned multiplier to a signed
    one?



    Thanks,

    Dan.





    LIBRARY IEEE; USE ieee.std_logic_1164.all;

    USE ieee.std_logic_arith.all;

    USE ieee.std_logic_unsigned.all;





    ENTITY serial_mac IS

    PORT (

    reset: IN STD_LOGIC;





    --[ XTAL OSCILLATOR INPUTS ]--

    x2: IN STD_LOGIC;





    --[ SERIAL MULTIPLIER CONTROL SIGNALS ]--

    multrst: IN STD_LOGIC;

    multavail: OUT STD_LOGIC;





    operand1: IN STD_LOGIC_VECTOR(7 downto 0);

    operand2: IN STD_LOGIC_VECTOR(7 downto 0);

    multres: BUFFER STD_LOGIC_VECTOR(15 downto 0)

    );

    END serial_mac;





    ARCHITECTURE behaviour OF serial_mac IS

    SIGNAL mac_enable: STD_LOGIC;

    SIGNAL multcnt: STD_LOGIC_VECTOR (3 downto 0);

    SIGNAL multtmp: STD_LOGIC_VECTOR (15 downto 0);

    BEGIN





    -------------------------------------------------------------------------
    -

    -- MULTIPLIER ENABLE PROCESS

    -------------------------------------------------------------------------
    -

    mac_en: PROCESS (reset, multrst, multcnt, mac_enable)

    BEGIN

    IF (reset = '0') OR (multcnt = 9) THEN -- reset or complete

    mac_enable <= '0'; -- disable multiply

    ELSIF (multrst = '1') THEN -- mult reset

    mac_enable <= '1'; -- enable multiply

    END IF;

    END PROCESS mac_en;





    -------------------------------------------------------------------------
    -

    -- SERIAL MULTIPLY PROCESS

    -------------------------------------------------------------------------
    -

    mac: PROCESS (mac_enable, x2, operand2, multres, multcnt)

    VARIABLE Bit: STD_LOGIC;

    BEGIN

    IF (mac_enable = '0') THEN -- multiply reset
    active

    multcnt <= (OTHERS => '0'); -- zero multiply count

    multres <= (OTHERS => '0'); -- zero mult result

    multtmp(15 downto 8) <= (OTHERS => '0'); -- clear upper bit

    multtmp(7 downto 0) <= operand2; -- load operand 2 to
    temp

    ELSIF rising_edge(x2) THEN -- rising edge of
    clock

    CASE multcnt IS

    WHEN "0000" => bit := operand1(0);

    WHEN "0001" => bit := operand1(1);

    WHEN "0010" => bit := operand1(2);

    WHEN "0011" => bit := operand1(3);

    WHEN "0100" => bit := operand1(4);

    WHEN "0101" => bit := operand1(5);

    WHEN "0110" => bit := operand1(6);

    WHEN "0111" => bit := operand1(7);

    WHEN others => bit := '0';

    END CASE;

    IF (bit = '1') THEN -- if we have a one

    multres <= multres + multtmp; -- add to result

    END IF;

    multtmp <= multtmp(14 downto 0) & '0'; -- shift to right

    multcnt <= multcnt + 1; -- increment count

    END IF;

    multavail <= multcnt(3); -- result if
    available

    END PROCESS mac;





    END behaviour;
    Ndf, Oct 2, 2006
    #1
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  2. Ndf schrieb:

    > Someone can show me how to transform this unsigned multiplier to a signed
    > one?


    * sign extension (a lot of overhead)
    * Baugh-Wooley algorithm
    * Booth-Encoding
    * res <= std_ulogic_vector(sigend(op_1) * signed(op2));

    Ralf
    Ralf Hildebrandt, Oct 2, 2006
    #2
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