unsigned + std_logic

Discussion in 'VHDL' started by aleksazr@gmail.com, May 26, 2012.

  1. Guest

    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    I have an adder with carry out as std_logic,
    and I have a number as unsigned.

    signal limit, originallimit : unsigned(14 downto 0);
    signal cy : std_logic;

    limit <= originallimit + cy;

    I have searched the net, but can't find out how to
    convert std_logic to unsigned.

    If I declare CY as unsigned(0 downto 0) then it works,
    but it complains on the ADDER side (also, it makes more
    sense to declare it as std_logic... right?)
    , May 26, 2012
    #1
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  2. Guest

    On Saturday, May 26, 2012 12:17:52 PM UTC+2, wrote:
    > use ieee.std_logic_1164.all;
    > use ieee.numeric_std.all;
    >
    > I have an adder with carry out as std_logic,
    > and I have a number as unsigned.
    >
    > signal limit, originallimit : unsigned(14 downto 0);
    > signal cy : std_logic;
    >
    > limit <= originallimit + cy;
    >
    > I have searched the net, but can't find out how to
    > convert std_logic to unsigned.
    >
    > If I declare CY as unsigned(0 downto 0) then it works,
    > but it complains on the ADDER side (also, it makes more
    > sense to declare it as std_logic... right?)


    OK, I got it to work by introducing another signal:
    signal cy2 : std_logic_vector(0 downto 0);

    cy2(0) <= cy;
    limit <= originallimit + unsigned(cy2);

    but its a bit clumsy.. any better way?
    , May 26, 2012
    #2
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  3. Anssi Saari Guest

    writes:

    > OK, I got it to work by introducing another signal:
    > signal cy2 : std_logic_vector(0 downto 0);
    >
    > cy2(0) <= cy;
    > limit <= originallimit + unsigned(cy2);
    >
    > but its a bit clumsy.. any better way?


    How about

    limit <= originallimit + 1 when cy = '1' else originallimit;
    Anssi Saari, May 28, 2012
    #3
  4. Guest

    Hi,
    Your expression is legal in VHDL-2008, numeric_std package.
    limit <= originallimit + cy;

    Many tools should support it now. OTOH, if not,
    you can use any of the following:
    limit <= originallimit + ("" & cy) ; -- "" = null array
    limit <= originallimit + (1 => cy) ; -- aggregate array
    limit <= originallimit + ('0' & cy) ; -- aggregate array

    Make sure to use the parentheses. In VHDL-2008, the last
    one will result in an error without them.

    Best,
    Jim Lewis
    SynthWorks
    , Jul 21, 2012
    #4
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