unsigned(), unsigned'(), to_unsigned()

Discussion in 'VHDL' started by Shannon, Feb 13, 2009.

  1. Shannon

    Shannon Guest

    Ok, I struggle with this each and every time. Can someone help
    clarify for me when each version of these is valid to use? They all
    look so similar to me but I have to randomly guess each time I want to
    use one type of signal with a different type of signal.

    TIA,
    Shannon
    Shannon, Feb 13, 2009
    #1
    1. Advertising

  2. Shannon

    Tim McBrayer Guest

    Shannon wrote:
    > Ok, I struggle with this each and every time. Can someone help
    > clarify for me when each version of these is valid to use? They all
    > look so similar to me but I have to randomly guess each time I want to
    > use one type of signal with a different type of signal.


    I'll give it a shot. I am assuming here that you are using either IEEE.NUMERIC_BIT or
    IEEE.NUMERIC_STD for the definition of signed/unsigned.

    unsigned(<expr>) is a type conversion, and part of the base language. A type conversion
    provides for explicit conversion between closely related types. Without considering
    user-defined types, <expr> will be one of: std_logic_vector, std_ulogic_vector, or signed.

    unsigned'(<expr>) is a qualified expression, and also part of the base language. It is
    used to explicitly provide the type and/or subtype of an expression. This is common when
    the type of <expr> is not known from the context, as perhaps with a bit string literal.
    This is less commonly needed than a type conversion, as VHDL is usually pretty good at
    figuring out from the context what e.g. the type of "00001111" needs to be.

    to_unsigned(<expr>, <size>) is a function in IEEE.NUMERIC_[STD|BIT] that accepts an <expr>
    of type NATURAL (a non-negative integer) and converts it to a unsigned vector of length
    <size>.

    Regards,
    --
    Tim McBrayer
    x4229
    Tim McBrayer, Feb 13, 2009
    #2
    1. Advertising

  3. Tim McBrayer wrote:
    > Shannon wrote: Re: unsigned(), unsigned'(), to_unsigned()
    >> Ok, I struggle with this each and every time. Can someone help
    >> clarify for me when each version of these is valid to use?



    If I declare my numeric registers as unsigned, signed or integer range,
    I don't need any of them.

    -- Mike Treseler
    Mike Treseler, Feb 13, 2009
    #3
  4. Jim Lewis wrote:
    > Mike
    >> If I declare my numeric registers as unsigned, signed or integer range,
    >> I don't need any of them.
    >>
    >> -- Mike Treseler

    >
    > Do you make your external data bus unsigned?


    Not for device pins.
    For everything else it's up to the designer.

    > I have been in the habit of making all top level signals
    > as std_logic_vector - hopefully just a historical thing that
    > was due to older ASIC synthesis tools strongly preferred
    > std_logic_vector over any other type at the top level).
    > As a result, I use type conversions when loading the
    > std_logic_vector data bus into my unsigned programmable timers.


    If I use one of your modules,
    I guess I will have to use conversions as well ;)

    -- Mike Treseler
    Mike Treseler, Feb 13, 2009
    #4
  5. Shannon

    Shannon Guest

    On Feb 13, 10:05 am, Jim Lewis <> wrote:
    > Mike
    >
    > > If I declare my numeric registers as unsigned, signed or integer range,
    > > I don't need any of them.

    >
    > >       -- Mike Treseler

    >
    > Do you make your external data bus unsigned?  It may carry
    > some untyped stuff and some unsigned as well.
    >
    > I have been in the habit of making all top level signals
    > as std_logic_vector - hopefully just a historical thing that
    > was due to older ASIC synthesis tools strongly preferred
    > std_logic_vector over any other type at the top level).
    >
    > As a result, I use type conversions when loading the
    > std_logic_vector data bus into my unsigned programmable timers.
    >
    > Jim
    > --


    Exactly my situation as well. Thank you for the help. I know I will
    still run into confusion on this problem. I've posted here many times
    when the synthesis tool can't figure out what type to choose for
    something ambiguous.

    Shannon
    Shannon, Feb 13, 2009
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Timo Freiberger
    Replies:
    3
    Views:
    943
    Bob Hairgrove
    Oct 30, 2004
  2. sivaji

    TO_UNSIGNED COMMAND in vhdl

    sivaji, Feb 15, 2008, in forum: VHDL
    Replies:
    0
    Views:
    3,419
    sivaji
    Feb 15, 2008
  3. seinal
    Replies:
    3
    Views:
    16,646
    jeppe
    Jun 6, 2008
  4. pozz
    Replies:
    12
    Views:
    738
    Tim Rentsch
    Mar 20, 2011
  5. Nick Bayard
    Replies:
    6
    Views:
    475
    nbayard
    Mar 15, 2013
Loading...

Share This Page