Unsupported error,& Right operand of "Divide" operator must be a power of 2..

Discussion in 'VHDL' started by Kim JM, Feb 29, 2004.

  1. Kim JM

    Kim JM Guest

    Hi,
    I have a question concerning vhdl error.
    I tried to solve the error but I am still in trouble.

    My code's errors are as follows:
    1st. Unsupported feature error: remainder[REM] operator
    2nd. Right operand of "Divide" operator must be a power of 2


    1st error was solved when I replace rem to another operator, but I
    don't know what's wrong with my syntax about "rem".
    2nd error... I couldn't understand where the error lied.



    My code is as follows:

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

    ENTITY test_core_8254_3th IS
    PORT (
    CLK : IN std_logic ;
    D : Buffer integer range 0 to 255;
    PA, PB : OUT std_logic
    );
    END test_core_8254_3th;

    ARCHITECTURE arc OF test_core_8254_3th IS
    BEGIN
    process(CLK,D)
    variable cnt: integer:= 0;
    begin
    if (CLK' event and CLK = '1') then
    cnt:= cnt+1;
    if (D rem 2)=0 then
    if (cnt<=(10000/(D/2))/4) then
    PA<='1';
    PB<='0';
    else
    PA<='Z';
    PB<='Z';
    cnt:=0;
    end if;
    end if;
    end if;
    end process;
    END arc;



    How can I resolve my problem?

    I would appreciate any helpful hint.
    (and I'm sorry for my poor English... ^^;)


    Kind regards
    KIM JM.
     
    Kim JM, Feb 29, 2004
    #1
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  2. Kim JM

    Riyaz Guest

    Is the error you receive from a synthesis tool or a simulation tool. I
    believe it is from a synthesis tool in which case you will probably have to
    instantiate dividers to sort the problem. Try to think about how the design
    is going to be implemented in hardware, although it can be very easy to get
    carried away using procedural constructs. Maybe a very good synthesis tool
    can derive some hardware from that but it is generally more efficient if you
    spend some time trying to derive a hardware structure than to write C-type
    language in VHDL (this latter case can sometimes work mind but can result in
    larger and slower hardware)
    "Galland" <> wrote in message news:SC39c.783$...
    > > if (D rem 2)=0 then
    > > if (cnt<=(10000/(D/2))/4) then

    >
    > Hi, first you must understand that modelling hardware through a

    description
    > language
    > is not like writing software, in your code the division is only done if it
    > is divided by a multiple of 2 but the code is synthesized as a hardware

    that
    > does the division (10000/(D/2)) whichever D it is, it cannot be

    "activated"
    > if D is multiple of 2 and deactivated to ensure correct operation if it is
    > not. In hardware (though i might be wrong here) it would be implemented as

    a
    > division that executes always but only gets to cnt (through a multiplexor)
    > if (D rem 2) is 0. This is hardware description, not software description,
    > though practice and trial-and-error heals anybody ;).
    >
    > Galland
    >
    >
    >
    >
     
    Riyaz, Apr 2, 2004
    #2
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