Unsupported error,& Right operand of "Divide" operator must be a power of 2..

[Kim JM]

Hi,
I have a question concerning vhdl error.
I tried to solve the error but I am still in trouble.

My code's errors are as follows:
1st. Unsupported feature error: remainder[REM] operator
2nd. Right operand of "Divide" operator must be a power of 2


1st error was solved when I replace rem to another operator, but I
don't know what's wrong with my syntax about "rem".
2nd error... I couldn't understand where the error lied.



My code is as follows:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY test_core_8254_3th IS
PORT (
CLK : IN std_logic ;
D : Buffer integer range 0 to 255;
PA, PB : OUT std_logic
);
END test_core_8254_3th;

ARCHITECTURE arc OF test_core_8254_3th IS
BEGIN
process(CLK,D)
variable cnt: integer:= 0;
begin
if (CLK' event and CLK = '1') then
cnt:= cnt+1;
if (D rem 2)=0 then
if (cnt<=(10000/(D/2))/4) then
PA<='1';
PB<='0';
else
PA<='Z';
PB<='Z';
cnt:=0;
end if;
end if;
end if;
end process;
END arc;



How can I resolve my problem?

I would appreciate any helpful hint.
(and I'm sorry for my poor English... ^^


Kind regards
KIM JM.

 

[Riyaz]

Is the error you receive from a synthesis tool or a simulation tool. I
believe it is from a synthesis tool in which case you will probably have to
instantiate dividers to sort the problem. Try to think about how the design
is going to be implemented in hardware, although it can be very easy to get
carried away using procedural constructs. Maybe a very good synthesis tool
can derive some hardware from that but it is generally more efficient if you
spend some time trying to derive a hardware structure than to write C-type
language in VHDL (this latter case can sometimes work mind but can result in
larger and slower hardware)