unused bits in signals

Discussion in 'VHDL' started by Thomas, Jul 6, 2003.

  1. Thomas

    Thomas Guest

    I have to talk to registers that are 8 bits, but some bits are totally
    unsused in them;

    I get tons of warning from the synthetizer, using Xilinx's tools

    for example:

    signal myregister : std_logic_vector(7 downto 0);

    but I am only using bit 2 and 3, but I need to have it 'formatted' over 8
    bits so that I can do: myregister <= my8bitdata and it ignores everything
    but the bits 2 and 3?

    in short I am trying to find a way to tell the tool: I care only about
    these bits, don't warn me about the others, I know I'm not using them.
     
    Thomas, Jul 6, 2003
    #1
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  2. Thomas

    Mario Trams Guest

    Thomas wrote:

    > I have to talk to registers that are 8 bits, but some bits are totally
    > unsused in them;
    >
    > I get tons of warning from the synthetizer, using Xilinx's tools
    >
    > for example:
    >
    > signal myregister : std_logic_vector(7 downto 0);
    >
    > but I am only using bit 2 and 3, but I need to have it 'formatted' over 8
    > bits so that I can do: myregister <= my8bitdata and it ignores everything
    > but the bits 2 and 3?


    Why not using

    signal myregister: std_logic_vector(3 downto 2);
    ....
    myregister <= my8bitdata(3 downto 2);

    ???

    Regards,
    Mario

    --
    ----------------------------------------------------------------------
    Digital Force / Mario Trams -chemnitz.de

    Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
    Dept. of Computer Science Tel.: (+49) 371 531 1660
    Chair of Computer Architecture Fax.: (+49) 371 531 1818
    ----------------------------------------------------------------------
     
    Mario Trams, Jul 6, 2003
    #2
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  3. Thomas

    Mario Trams Guest

    Thomas wrote:

    >> Why not using
    >>
    >> signal myregister: std_logic_vector(3 downto 2);

    >
    > I didn't realize you could do that!; for some reason, I was assuming that
    > things had to either start or end at 0; that's going to help, I have so
    > many warnings all over the place; is there a syntax to do something like
    > that : std_logic_vector(5 downto 4, 2 downto 1) /


    I've never used it and I have never heard about it.
    Check some documentation!

    Regards,
    Mario

    --
    ----------------------------------------------------------------------
    Digital Force / Mario Trams -chemnitz.de

    Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
    Dept. of Computer Science Tel.: (+49) 371 531 1660
    Chair of Computer Architecture Fax.: (+49) 371 531 1818
    ----------------------------------------------------------------------
     
    Mario Trams, Jul 6, 2003
    #3
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