Thank you for your reply,
There was one component which I was reusing twice, once using all of the
outputs and another time using only half of them. Basically when you reuse
VHDL components you often don't want to use all of the inputs and outputs
available in that component. Al least not for quick-and-dirty designs.
Furthermore, in some board-level designs it may be the case that
purchasing several identical larger components that can perform
several functions is cheper than purchasing many more smaller
components that perform smaller tasks but are all different
from each other, because you may get bulk discounts by
purchasing larger but identical components.
For instance consider a VHDL design that makes use of a VHDL component
that implements the famous 74-series medium scale integration 74x157
multiplexer. This device has an active-low enable input (G) which
can be connected to the ground, two four-input vector
A = (4A, 3A, 2A, 1A)
and
B = (4B, 3B, 2B, 1B)
and an outut vector
Y = (4Y, 3Y, 2Y, 1Y)
The 74x157, being a MUX, also has a selection line, which consists of a
single signal, S, such that the output Y of the 74x157 is A when S = 0 and
the output Y is equal to B when S = 1.
So here we have a device that could be instantiated in such a way that the
S input is connected to ground and the B inputs are disconnected, since
they are not needed. Similarly, it could be that we are only interested
in half of the A values, say 1A and 2A, with 3A and 4A being disconnected.
Certainly in all of these cases diconnecting the wires is certainly not
useless and is what is meant: we want to use some component that we have
multiple copies of but don't need to use all of its wires.
So, it seems strange to me that VHDL would not have a construct such that
you could say something like the following (untested) code:
library ieee;
use ieee.std_logic_1164.all;
entity Foo is
port (
FoosS: in std_ulogic;
FoosA: in std_ulogic_vector(4 downto 1);
FoosY: out std_ulogic_vector(4 downto 1)
-- more stuff here
);
end entity Foo;
architecture arch of Foo is
component Mux74x157 is
port (
G: in std_ulogic;
S: in std_ulogic;
A: in std_ulogic_vector(4 downto 1);
B: in std_ulogic_vector(4 downto 1);
Y: out std_ulogic_vector(4 downto 1)
);
end component Mux74x157;
-- more stuff here
begin
U: Mux74x157
port map (
G => 0,
S => FoosS,
A => FoosA,
B => disconnected,
T => FoosY
);
end architecture arch;
library ieee;
use ieee.std_logic_1164.all;
entity Mux74x157 is
port (
G: in std_ulogic;
S: in std_ulogic;
A: in std_ulogic_vector(4 downto 1);
B: in std_ulogic_vector(4 downto 1);
Y: out std_ulogic_vector(4 downto 1)
);
end entity Mux74x157;
architecture arch of Mux74x157 is
begin
with S select
Y <=
A when '0',
B when '1',
"UUUU" when others;
end architecture arch;