USB vhdl code

Discussion in 'VHDL' started by Antti Lukats, May 31, 2004.

  1. Antti Lukats

    Antti Lukats Guest

    "Paolo Santinelli" <> wrote in message
    news:c9f6dq$91o$...
    > I am Paolo Santinelli, I am a teacher, I have a laboratory course on
    > computer architecture and FPGA at the University of Modena and Reggio
    > Emilia, Italy. I am looking for a USB vhdl synthesizable model to use in

    my
    > course.
    >
    > Should you gave me some helps ?


    There is only one free VHDL USB core from someone in Japan. It does
    synthesize, but I have not verified it in FPGA. All others (free open
    source) are in verilog. As to my knowledge non of the free version are fully
    compliant to the usb specification at this time. Well for university course
    and educational use that doesnt matter.

    Antti

    SL811HST-AC
    http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=3818512873
     
    Antti Lukats, May 31, 2004
    #1
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  2. I am Paolo Santinelli, I am a teacher, I have a laboratory course on
    computer architecture and FPGA at the University of Modena and Reggio
    Emilia, Italy. I am looking for a USB vhdl synthesizable model to use in my
    course.



    Should you gave me some helps ?




    Thanks in advance.




    Paolo Santinelli.
     
    Paolo Santinelli, May 31, 2004
    #2
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  3. OpenCores has USB implementations (1.1 and 2.0). I didn't check if
    they're complete or synthesizeable, but I would guess so.
    Surely worth a look: http://www.opencores.com

    USB 2.0 Function Core:
    http://www.opencores.com/projects.cgi/web/usb/overview

    USB 1.1 PHY:
    http://www.opencores.com/projects.cgi/web/usb_phy/overview

    USB 1.1 Function Core:
    http://www.opencores.com/projects.cgi/web/usb1_funct/overview

    SystemC USB 1.1 IP Core:
    http://www.opencores.com/projects.cgi/web/usb11/overview

    Greetings,
    CM Wintersteiger

    On Mon, 31 May 2004 13:44:08 +0200, "Paolo Santinelli"
    <> wrote:

    > I am Paolo Santinelli, I am a teacher, I have a laboratory course on
    >computer architecture and FPGA at the University of Modena and Reggio
    >Emilia, Italy. I am looking for a USB vhdl synthesizable model to use in my
    >course.
    >
    >
    >
    >Should you gave me some helps ?
    >
    >
    >
    >
    >Thanks in advance.
    >
    >
    >
    >
    >Paolo Santinelli.
    >
    >
    >
    >
    >
    >
    >
     
    Christoph M. Wintersteiger, May 31, 2004
    #3
  4. Antti Lukats

    SgimS Guest

    caro professore...beccato a copiare eh????


    "Paolo Santinelli" <> ha scritto nel messaggio
    news:c9f6dq$91o$...
    > I am Paolo Santinelli, I am a teacher, I have a laboratory course on
    > computer architecture and FPGA at the University of Modena and Reggio
    > Emilia, Italy. I am looking for a USB vhdl synthesizable model to use in

    my
    > course.
    >
    >
    >
    > Should you gave me some helps ?
    >
    >
    >
    >
    > Thanks in advance.
    >
    >
    >
    >
    > Paolo Santinelli.
    >
    >
    >
    >
    >
    >
    >
    >
     
    SgimS, May 31, 2004
    #4
  5. Antti Lukats

    Fabio G. Guest

    "SgimS" <> ha scritto:

    >caro professore...beccato a copiare eh????


    E oltretutto l'inglese non e' nemmeno impeccabile! ;-))))

    --
    Per rispondermi via email sostituisci il risultato
    dell'operazione (in lettere) dall'indirizzo
     
    Fabio G., May 31, 2004
    #5
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