use clause

Discussion in 'VHDL' started by crazyrdx, Aug 30, 2005.

  1. crazyrdx

    crazyrdx Guest

    I would like to know why is it that in some of the VHDL code I have
    seen, the USE clauses are defined at various points in the program,
    instead of all at the beginning. In fact, there is even seeming to be a
    repetition of some of the use clauses within one program(like before
    entity declaration and then again before architecture definition). Why
    is this?

    Thanks
    crazyrdx, Aug 30, 2005
    #1
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  2. crazyrdx

    Guest

    You need a use clause for each package and for each entity/architecture
    pair (placed before the entity). I am not a VHDL guru, but I'm sure it
    has to do with the scope of a use statement.
    , Aug 30, 2005
    #2
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