Use of generics at top level of testbench

Discussion in 'VHDL' started by gizmo, Dec 11, 2008.

  1. gizmo

    gizmo

    Joined:
    Dec 11, 2008
    Messages:
    1
    hi all,
    I have been having a look around and although there are a few posts concerning this I still havent found a real answer. Could someone please give me some help or point me in the right direction?

    I am trying to perfrom conditional compilation using a generic to control which components of my testbench are included on a testcase by testcase basis.

    Basically i am using configurations to setup my testbench for testcases and would like to be able to set a generic to control which components are included. I am planning to use generate statements within an 'if' to control the generation of componants (the reason is to reduce simulation times for quick checks and then release this for over night runs).

    I have used generics to pass values to components within my testbench but am unsure how to do this at the top level so any help would be much appreciated.

    If it helps heres a sample of one of my configurations

    configuration 1 of testbenchtop is
    for structure

    for inst : tb_comp_1
    use entity tb_lib.tb_comp_1(rtl)
    generic map(...);
    end for;

    for inst_dut: dut
    use entity work.dut(rtl)
    generic map (..);
    end for;
    end for;
    end 1;

    any help would be much appreciated, thanks in advance
    G
    gizmo, Dec 11, 2008
    #1
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