Use of multiple processes in one source

Discussion in 'VHDL' started by illogical, Sep 3, 2006.

  1. illogical

    illogical Guest

    Relative new guy to VHDL here, trying to get my head around it (coming
    from a procedural/OO background).

    Trying to implement a basic ALU, 5 operations with 5 individual input
    gates to indicate they are selected.

    I was aiming to use 5 PROCESS statements to 'trigger' when one of the
    bits is set high, is this feasible in VHDL? (example below).

    architecture Behavioral of alu is
    begin
    do_add: process (data_a, data_b, op_add) -- add
    begin
    if op_add = '1' then
    y <= data_a + data_b;
    end if; end process do_add;

    do_sub: process (data_a, data_b, op_comp) -- complement
    begin
    if op_sub = '1' then
    y <= not(data_a)
    end if;
    end process do_sub;

    ... and so on.


    Or is it 'better practice' to do with multiple if then else statements?
    The result is a combinational circuit ether way, but I'm unfamiliar with
    the ins and outs of VHDL just yet.

    P.S Can't change the way the operation is specified, i.e. must 5
    seperate signals rather than one "op code" signal.
     
    illogical, Sep 3, 2006
    #1
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  2. illogical

    illogical Guest

    illogical wrote:
    > do_sub: process (data_a, data_b, op_comp) -- complement
    > begin
    > if op_sub = '1' then
    > y <= not(data_a)
    > end if;
    > end process do_sub;
    >
    > .. and so on.
    >


    Ugh, obviously stuffed up the copy/paste: should be the complement
    operation

    do_comp: process (data_a, data_b, op_comp) -- complement
    begin
    if op_comp = '1' then
    y <= not(data_a)
    end if;
    end process do_comp;
     
    illogical, Sep 3, 2006
    #2
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  3. illogical

    EvilTche Guest

    You've a multi-source problem with your design, you should use only one
    single process to assign value to the y signal.

    process(data_a, data_b, op_comp)
    begin
    if cond1 then
    y <= something;
    elsif cond2 then
    y <= otherthing;
    ...
    end if;
    end process;

    illogical wrote:
    > illogical wrote:
    > > do_sub: process (data_a, data_b, op_comp) -- complement
    > > begin
    > > if op_sub = '1' then
    > > y <= not(data_a)
    > > end if;
    > > end process do_sub;
    > >
    > > .. and so on.
    > >

    >
    > Ugh, obviously stuffed up the copy/paste: should be the complement
    > operation
    >
    > do_comp: process (data_a, data_b, op_comp) -- complement
    > begin
    > if op_comp = '1' then
    > y <= not(data_a)
    > end if;
    > end process do_comp;
     
    EvilTche, Sep 3, 2006
    #3
  4. illogical

    EvilTche Guest

    You'd also consider describing syncronous designs, if you're not
    familiar with digital circuits designs, I strongly recommend you start
    studying.

    EvilTche wrote:
    > You've a multi-source problem with your design, you should use only one
    > single process to assign value to the y signal.
    >
    > process(data_a, data_b, op_comp)
    > begin
    > if cond1 then
    > y <= something;
    > elsif cond2 then
    > y <= otherthing;
    > ...
    > end if;
    > end process;
    >
    > illogical wrote:
    > > illogical wrote:
    > > > do_sub: process (data_a, data_b, op_comp) -- complement
    > > > begin
    > > > if op_sub = '1' then
    > > > y <= not(data_a)
    > > > end if;
    > > > end process do_sub;
    > > >
    > > > .. and so on.
    > > >

    > >
    > > Ugh, obviously stuffed up the copy/paste: should be the complement
    > > operation
    > >
    > > do_comp: process (data_a, data_b, op_comp) -- complement
    > > begin
    > > if op_comp = '1' then
    > > y <= not(data_a)
    > > end if;
    > > end process do_comp;
     
    EvilTche, Sep 3, 2006
    #4
  5. On Sun, 03 Sep 2006 16:23:26 +1000, illogical <> wrote:

    >Relative new guy to VHDL here, trying to get my head around it (coming
    >from a procedural/OO background).
    >
    >Trying to implement a basic ALU, 5 operations with 5 individual input
    >gates to indicate they are selected.
    >
    >I was aiming to use 5 PROCESS statements to 'trigger' when one of the
    >bits is set high, is this feasible in VHDL? (example below).


    This creates 5 separate drivers for the "y" signal - unless "y" is a
    specific resolved type, all 5 outputs are effectively shorted together.
    There are circumstances when you might want to do this, but an ALU is
    not typically one of them.

    >architecture Behavioral of alu is
    >begin
    > do_add: process (data_a, data_b, op_add) -- add
    > begin
    > if op_add = '1' then
    > y <= data_a + data_b;
    > end if; end process do_add;
    >
    > do_sub: process (data_a, data_b, op_comp) -- complement
    > begin
    > if op_sub = '1' then
    > y <= not(data_a)
    > end if;
    > end process do_sub;
    >
    >.. and so on.
    >
    >
    >Or is it 'better practice' to do with multiple if then else statements?
    >The result is a combinational circuit ether way, but I'm unfamiliar with
    >the ins and outs of VHDL just yet.


    Good practice is to state your intent as clearly as you can.

    If the intent is to produce one ALU reacting to only one op out of a set
    of ops at any time, code it that way - a single process implementing a
    "case" statement on the set of ops. A sequence of "if" statements works
    too, but encodes priority differently, if (e.g) more than one op is
    asserted.

    It'll be clearer and smaller that way too. And more familiar to a
    procedural programmer.

    If the intent is to increase parallelism, e.g. to issue "add" and "sub"
    ops simultaneously, and use the separate outputs independently of each
    other, you need separate output signals (e.g. y_add, y_sub etc) for each
    process. Then separate processes will work just fine, but so will
    separate outputs (e.g. from separate "if" statements) within the same
    process. This is where you start to think HDL rather than procedurally.

    >P.S Can't change the way the operation is specified, i.e. must 5
    >seperate signals rather than one "op code" signal.


    They can however be aggregated into one signal

    op <= op_add & op_sub & ... ;

    Which doesn't prevent the ALU's user asserting more than one.
    If he does, what does he expect to happen? That is crucial information
    to determine how you should implement the ALU.

    Note that the case statement provides a "when others" clause to cover
    the defaults and unspecified cases.

    - Brian
     
    Brian Drummond, Sep 3, 2006
    #5
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