use work.my_package.all-->what exactly meaning of this

Discussion in 'VHDL' started by Parthav, Jan 11, 2006.

  1. Parthav

    Parthav Guest

    Hello friends,

    I'm not the novice for the VHDL coding but i've not came across adding
    the use work.my_package.all in the initial library declaration part.

    Now i want help on that what exactly this statement do? Also if i'm
    making a function in the package body where i should store the file and
    with which extension? Here i'm giving you the code on which i'm working
    right now.

    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;
    library work;
    use work.my_package.all;

    entity multiplier1 is
    generic (size: integer := 4);
    Port ( a,b : in unsigned(size-1 downto 0);
    --b : in std_logic;
    y : out unsigned(2*size-1 downto 0));
    end multiplier1;

    architecture Behavioral of multiplier1 is

    begin
    y <= mult(a,b);

    end Behavioral;


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    package pack is
    function mult(a,b:unsigned) return unsigned;
    end pack;

    package body pack is
    function mult(a,b:unsigned)return unsigned is
    constant max:integer := a'length + b'length -1;
    variable aa:unsigned(max downto 0) := (max downto a'length => '0') &
    a(a'length-1 downto 0);
    variable prod:unsigned(max downto 0) := (others => '0');
    begin
    for i in 0 to a'length-1 loop
    if (b(i)='1') then prod:=prod+aa;
    end if;
    aa := aa(max-1 downto 0) & '0';
    end loop;
    return prod;
    end mult;
    end pack;

    Regards..

    Parthav
     
    Parthav, Jan 11, 2006
    #1
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  2. Parthav

    john Doef Guest

    Parthav a écrit :

    > Hello friends,
    >
    > I'm not the novice for the VHDL coding but i've not came across adding
    > the use work.my_package.all in the initial library declaration part.
    >
    > Now i want help on that what exactly this statement do?

    It makes all declarations of the package potentially visible.
    (BTW, this is not a statement but a context clause).
    This clause is almost *never* necessary: each place you use a
    declaration from
    your package, you can replace the name with its expanded form:
    work.my_package.my_func (x , y) instead of my_func (x, y).

    > Also if i'm
    > making a function in the package body where i should store the file and
    > with which extension? Here i'm giving you the code on which i'm working
    > right now.

    VHDL almost ignore the problem of files: ie you can almost do what you
    want.
    However, the package must be analyzed before the design unit which uses
    it.

    JD.
     
    john Doef, Jan 12, 2006
    #2
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  3. Parthav

    Jim Lewis Guest

    Parthav,
    Right off, I see 2 problems:
    1) The statement "use work.my_package.all" references
    a package named "my_package". You named your package
    "pack".
    2)
    If these are in the same file, put your packge before your entity.
    VHDL requires a referenced design unit to be compiled.

    Cheers,
    Jim

    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    > Hello friends,
    >
    > I'm not the novice for the VHDL coding but i've not came across adding
    > the use work.my_package.all in the initial library declaration part.
    >
    > Now i want help on that what exactly this statement do? Also if i'm
    > making a function in the package body where i should store the file and
    > with which extension? Here i'm giving you the code on which i'm working
    > right now.
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    > library work;
    > use work.my_package.all;
    >
    > entity multiplier1 is
    > generic (size: integer := 4);
    > Port ( a,b : in unsigned(size-1 downto 0);
    > --b : in std_logic;
    > y : out unsigned(2*size-1 downto 0));
    > end multiplier1;
    >
    > architecture Behavioral of multiplier1 is
    >
    > begin
    > y <= mult(a,b);
    >
    > end Behavioral;
    >
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.ALL;
    > use IEEE.STD_LOGIC_ARITH.ALL;
    > use IEEE.STD_LOGIC_UNSIGNED.ALL;
    >
    > package pack is
    > function mult(a,b:unsigned) return unsigned;
    > end pack;
    >
    > package body pack is
    > function mult(a,b:unsigned)return unsigned is
    > constant max:integer := a'length + b'length -1;
    > variable aa:unsigned(max downto 0) := (max downto a'length => '0') &
    > a(a'length-1 downto 0);
    > variable prod:unsigned(max downto 0) := (others => '0');
    > begin
    > for i in 0 to a'length-1 loop
    > if (b(i)='1') then prod:=prod+aa;
    > end if;
    > aa := aa(max-1 downto 0) & '0';
    > end loop;
    > return prod;
    > end mult;
    > end pack;
    >
    > Regards..
    >
    > Parthav
     
    Jim Lewis, Jan 12, 2006
    #3
  4. Parthav

    Parthav Guest

    Thanks Jim and John,thanks a lot.

    but main thing is that i'm not able to synthesize it as the compiler
    shows me the error "Unknown predefined function 'mult' of package
    'std_logic_arith' ".

    I've tried a lot but unable to traceout the error and the ofcourse
    possible cause of it.

    I wish you can help me this time also.

    Once again thanks for your help Jim.

    Regards..

    Parthav
     
    Parthav, Jan 13, 2006
    #4
  5. Parthav wrote:

    > but main thing is that i'm not able to synthesize it as the compiler
    > shows me the error "Unknown predefined function 'mult' of package
    > 'std_logic_arith' ".
    > I've tried a lot but unable to traceout the error and the ofcourse
    > possible cause of it.


    You would need a vhdl simulator to debug this.

    You have to compile the package before
    you use it, or else get rid of it (see z below)

    -- Mike Treseler
    _________________________________________________
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    package pack is
    constant len_c : natural := 4;
    function mult(a, b : unsigned) return unsigned;
    end pack;
    package body pack is
    function mult(a, b : unsigned)return unsigned is
    constant max : integer := a'length + b'length -1;
    variable aa : unsigned(max downto 0) :=
    (max downto a'length => '0') &
    a(a'length-1 downto 0);
    variable prod : unsigned(max downto 0) := (others => '0');
    begin
    for i in 0 to a'length-1 loop
    if (b(i) = '1') then prod := prod+aa;
    end if;
    aa := aa(max-1 downto 0) & '0';
    end loop;
    return prod;
    end mult;
    end pack;
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use work.pack.all;
    entity multiplier1 is
    generic (size : integer := 4);
    port (a, b : in unsigned(size-1 downto 0);
    y,z : out unsigned(2*size-1 downto 0));
    end multiplier1;
    architecture Behavioral of multiplier1 is
    begin
    y <= mult(a, b); -- hard way: infers muxes and adders
    z <= a*b; -- easy way: infers a multipler
    end Behavioral;
     
    Mike Treseler, Jan 13, 2006
    #5
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