using 2 diffrent clock rates in a design.

Discussion in 'VHDL' started by Abs, Jan 25, 2006.

  1. Abs

    Abs Guest

    Hi friends.
    how r u all doing,
    well i have a doubt here. i have to write a tcl script to produce an
    input from a file at a clock rate "clk1" and then capture the output of
    the DUT at a diffrent clock rate say "clk2". now i have to give input
    to DUT at a while loop and then capture at a diffrent loop. i'am facing
    problem here/
    any clues or ideas how to proceed..
    plzz reply soon..

    thanks

    bye
     
    Abs, Jan 25, 2006
    #1
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