Using a global clock as an enable for flip-flops and RAMs?

Discussion in 'VHDL' started by mav1101, Sep 18, 2006.

  1. mav1101

    mav1101 Guest

    Hi all,

    I've heard that a good rule of thumb is to not to use a global clock as
    an enable for flops. I'm currently working with a Xilinx Virtex FPGA
    and I'm trying to solve a crossover circuit to interface an internal
    module with a Virtex BlockSelect DPRAM. The crossover is needed to
    satisfy the RAM appnote requiring a skew between the porta and portb
    clocks. I cannot change the interfacing module nor the the opposite
    port clock on the DPRAM. The solution that I have consists of doing a
    crossover and using one of the clocks as an enable for both the DPRAM
    and some of the flops in the crossover circuit. Even though the
    solution seems to work in post place and route simulation, I'm getting
    warning messages in Xilinx ISE because I'm connecting clocks to
    non-clock inputs. Static timing numbers look ok too. Neverthless, I'm
    wondering if this a problem (i.e. adding loading to the clock tree)?

    Any advice would be greatly appreciated.

    Cheers,
    mav1101, Sep 18, 2006
    #1
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  2. mav1101

    Dave Dean Guest

    I've run into this before in a design where I ran the clock through a mux
    before sending it to an output pin. Xilinx AR #22997 makes some mention of
    the warning. My understanding is that the non-clock pin connection adds a
    lot of skew to the overall clock net, but won't actually effect the skew
    when considering only the clock pins. So, if youre static timing numbers
    look good for registers that are actually clocked by the clock, I think
    you're ok.
    Any other opinions?
    Dave

    "mav1101" <> wrote in message
    news:...
    > Hi all,
    >
    > I've heard that a good rule of thumb is to not to use a global clock as
    > an enable for flops. I'm currently working with a Xilinx Virtex FPGA
    > and I'm trying to solve a crossover circuit to interface an internal
    > module with a Virtex BlockSelect DPRAM. The crossover is needed to
    > satisfy the RAM appnote requiring a skew between the porta and portb
    > clocks. I cannot change the interfacing module nor the the opposite
    > port clock on the DPRAM. The solution that I have consists of doing a
    > crossover and using one of the clocks as an enable for both the DPRAM
    > and some of the flops in the crossover circuit. Even though the
    > solution seems to work in post place and route simulation, I'm getting
    > warning messages in Xilinx ISE because I'm connecting clocks to
    > non-clock inputs. Static timing numbers look ok too. Neverthless, I'm
    > wondering if this a problem (i.e. adding loading to the clock tree)?
    >
    > Any advice would be greatly appreciated.
    >
    > Cheers,
    >
    Dave Dean, Sep 22, 2006
    #2
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