Using a memory initialization file

Discussion in 'VHDL' started by Walther, Feb 16, 2009.

  1. Walther

    Walther Guest

    I apologize in advance for what is probably a really stupid beginners
    question.

    I am currently busy with an assignment for my one course. We are
    required to implement the RiSC-16 sequential CPU in VHDL using Quartus
    II. We are however not allowed to use megafunctions or other altera
    supplied libraries.

    Now, my CPU is pretty much done. I am however struggling to figure out
    how to link a MIF file to a specific memory component (Namely to my
    instruction memory component).

    Does anybody know how to do this, and could you please give a nice
    step by step explanation on how to do it.

    Thanks in advance.
    Walther
     
    Walther, Feb 16, 2009
    #1
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  2. Walther

    Aiken Guest

    do you do it in your simulation program for example Modelsim.
    After you start your simluation at time "0". you can update the memory
    content.

    Aiken

    On Feb 16, 3:22 pm, Walther <> wrote:
    > I apologize in advance for what is probably a really stupid beginners
    > question.
    >
    > I am currently busy with an assignment for my one course. We are
    > required to implement the RiSC-16 sequential CPU in VHDL using Quartus
    > II. We are however not allowed to use megafunctions or other altera
    > supplied libraries.
    >
    > Now, my CPU is pretty much done. I am however struggling to figure out
    > how to link a MIF file to a specific memory component (Namely to my
    > instruction memory component).
    >
    > Does anybody know how to do this, and could you please give a nice
    > step by step explanation on how to do it.
    >
    > Thanks in advance.
    > Walther
     
    Aiken, Feb 16, 2009
    #2
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  3. Walther wrote:

    > I am currently busy with an assignment for my one course. We are
    > required to implement the RiSC-16 sequential CPU in VHDL using Quartus
    > II. We are however not allowed to use megafunctions or other altera
    > supplied libraries.


    That is a good thing.
    You won't learn to write code using megafunctions.

    > Now, my CPU is pretty much done. I am however struggling to figure out
    > how to link a MIF file to a specific memory component (Namely to my
    > instruction memory component).


    Maybe you don't need a mif file.
    Why not infer a rom from a vhdl constant array?
    Something like this
    http://mysite.verizon.net/miketreseler/sync_rom.vhd

    -- Mike Treseler
     
    Mike Treseler, Feb 16, 2009
    #3
  4. Walther

    Walther Guest

    On Feb 17, 1:30 am, Mike Treseler <> wrote:
    > Walther wrote:
    > > I am currently busy with an assignment for my one course. We are
    > > required to implement the RiSC-16 sequential CPU in VHDL using Quartus
    > > II. We are however not allowed to use megafunctions or other altera
    > > supplied libraries.

    >
    > That is a good thing.
    > You won't learn to write code using  megafunctions.
    >
    > > Now, my CPU is pretty much done. I am however struggling to figure out
    > > how to link a MIF file to a specific memory component (Namely to my
    > > instruction memory component).

    >
    > Maybe you don't need a mif file.
    > Why not infer a rom from a vhdl constant array?
    > Something like thishttp://mysite.verizon.net/miketreseler/sync_rom.vhd
    >
    >    -- Mike Treseler


    Thanks Mike

    That is what I'm currently doing to test the CPU. However, I would
    like to be able to easily load other test programs without needing to
    retype all the instructions and recompiling. If I can't initialise the
    memory from an external file, then it's not a train smash, but it
    would make verification and simulation much easier.

    Walther
     
    Walther, Feb 17, 2009
    #4
  5. Walther

    Tricky Guest

    On 17 Feb, 06:43, Walther <> wrote:
    > On Feb 17, 1:30 am, Mike Treseler <> wrote:
    >
    >
    >
    > > Walther wrote:
    > > > I am currently busy with an assignment for my one course. We are
    > > > required to implement the RiSC-16 sequential CPU in VHDL using Quartus
    > > > II. We are however not allowed to use megafunctions or other altera
    > > > supplied libraries.

    >
    > > That is a good thing.
    > > You won't learn to write code using  megafunctions.

    >
    > > > Now, my CPU is pretty much done. I am however struggling to figure out
    > > > how to link a MIF file to a specific memory component (Namely to my
    > > > instruction memory component).

    >
    > > Maybe you don't need a mif file.
    > > Why not infer a rom from a vhdl constant array?
    > > Something like thishttp://mysite.verizon.net/miketreseler/sync_rom.vhd

    >
    > >    -- Mike Treseler

    >
    > Thanks Mike
    >
    > That is what I'm currently doing to test the CPU. However, I would
    > like to be able to easily load other test programs without needing to
    > retype all the instructions and recompiling. If I can't initialise the
    > memory from an external file, then it's not a train smash, but it
    > would make verification and simulation much easier.
    >
    > Walther


    Then you will probably have to write a script to write the constant
    array for you, to then copy/paste into your code - or for even more
    clvereness, actaully re-write the constant declaration for you inside
    the VHDL.

    Otherwise, you will have to write your own MIF interpreter, which will
    probably be just as involved as the above idea.
     
    Tricky, Feb 17, 2009
    #5
  6. Walther

    Barry Guest

    On Feb 16, 12:22 pm, Walther <> wrote:
    > I apologize in advance for what is probably a really stupid beginners
    > question.
    >
    > I am currently busy with an assignment for my one course. We are
    > required to implement the RiSC-16 sequential CPU in VHDL using Quartus
    > II. We are however not allowed to use megafunctions or other altera
    > supplied libraries.
    >
    > Now, my CPU is pretty much done. I am however struggling to figure out
    > how to link a MIF file to a specific memory component (Namely to my
    > instruction memory component).
    >
    > Does anybody know how to do this, and could you please give a nice
    > step by step explanation on how to do it.
    >
    > Thanks in advance.
    > Walther


    I only used a mif file once, when I used Xilinx CoreGen to create a
    ROM. I just dragged the mif file into my testbench directory (which
    is the directory I opened in ModelSim to run the simulation), and it
    picked up the mif file automatically.

    Barry
     
    Barry, Feb 17, 2009
    #6
  7. Walther

    PlayDough Guest

    On Feb 17, 1:12 am, Tricky <> wrote:
    > Then you will probably have to write a script to write the constant
    > array for you, to then copy/paste into your code - or for even more
    > clvereness, actaully re-write the constant declaration for you inside
    > the VHDL.


    Or rather, write a Perl script or C program to convert the MIF into a
    format that is easy to import. It is quite easy to write some VHDL to
    read in a simple list of vectors from a file to populate your RAM. I
    recommend you look at the source code for the Altera primitive RAM
    models. I've never used Altera, but both Xilinx and Actel models are
    capable of being initialized from a file, and the code is very easy to
    understand.

    I've never heard of MIF until this thread, but it looks very easy to
    parse. (I used the reference at the Altera site:
    http://www.altera.com/support/software/nativelink/quartus2/glossary/def_mif..html).
    And considering that Altera is the source, their models probably read
    MIF files. So you can scab the code from their models.

    > Otherwise, you will have to write your own MIF interpreter, which will
    > probably be just as involved as the above idea.


    Doing this in VHDL/Verilog (though perhaps with the PLI it could be
    fairly simple) would be more difficult than a Perl script/C code to
    generate the constant table. For a class, I recommend a script based
    approach.

    Pete
     
    PlayDough, Feb 17, 2009
    #7
  8. Walther

    Amal Guest

    On Feb 17, 1:15 pm, PlayDough <> wrote:
    > On Feb 17, 1:12 am, Tricky <> wrote:
    >
    > > Then you will probably have to write a script to write the constant
    > > array for you, to then copy/paste into your code - or for even more
    > > clvereness, actaully re-write the constant declaration for you inside
    > > the VHDL.

    >
    > Or rather, write a Perl script or C program to convert the MIF into a
    > format that is easy to import.  It is quite easy to write some VHDL to
    > read in a simple list of vectors from a file to populate your RAM.  I
    > recommend you look at the source code for the Altera primitive RAM
    > models.  I've never used Altera, but both Xilinx and Actel models are
    > capable of being initialized from a file, and the code is very easy to
    > understand.
    >
    > I've never heard of MIF until this thread, but it looks very easy to
    > parse.  (I used the reference at the Altera site:http://www.altera.com/support/software/nativelink/quartus2/glossary/d...).
    > And considering that Altera is the source, their models probably read
    > MIF files.  So you can scab the code from their models.
    >
    > > Otherwise, you will have to write your own MIF interpreter, which will
    > > probably be just as involved as the above idea.

    >
    > Doing this in VHDL/Verilog (though perhaps with the PLI it could be
    > fairly simple) would be more difficult than a Perl script/C code to
    > generate the constant table.  For a class, I recommend a script based
    > approach.
    >
    > Pete


    If you are using Synplicity and do not mind using Verilog for your
    ROMs, you can use $readmemb, $readmemh tasks in an initial block to
    read the contents of ROM from the file. This way you can have a
    portable ROM implementation between FPGA and ASIC versions. For FPGA
    version, $readmemb, and $redmemh use the same memory data file as your
    ASIC foundry's ROM data file.

    Check and see if Quartus supports $readmemb or $readmemh for
    synthesis.

    -- Amal
     
    Amal, Feb 18, 2009
    #8
  9. Walther

    Walther Guest

    On Feb 18, 5:31 pm, Amal <> wrote:
    > On Feb 17, 1:15 pm, PlayDough <> wrote:
    >
    >
    >
    > > On Feb 17, 1:12 am, Tricky <> wrote:

    >
    > > > Then you will probably have to write a script to write the constant
    > > > array for you, to then copy/paste into your code - or for even more
    > > > clvereness, actaully re-write the constant declaration for you inside
    > > > the VHDL.

    >
    > > Or rather, write a Perl script or C program to convert the MIF into a
    > > format that is easy to import.  It is quite easy to write some VHDL to
    > > read in a simple list of vectors from a file to populate your RAM.  I
    > > recommend you look at the source code for the Altera primitive RAM
    > > models.  I've never used Altera, but both Xilinx and Actel models are
    > > capable of being initialized from a file, and the code is very easy to
    > > understand.

    >
    > > I've never heard of MIF until this thread, but it looks very easy to
    > > parse.  (I used the reference at the Altera site:http://www.altera.com/support/software/nativelink/quartus2/glossary/d...).
    > > And considering that Altera is the source, their models probably read
    > > MIF files.  So you can scab the code from their models.

    >
    > > > Otherwise, you will have to write your own MIF interpreter, which will
    > > > probably be just as involved as the above idea.

    >
    > > Doing this in VHDL/Verilog (though perhaps with the PLI it could be
    > > fairly simple) would be more difficult than a Perl script/C code to
    > > generate the constant table.  For a class, I recommend a script based
    > > approach.

    >
    > > Pete

    >
    > If you are using Synplicity and do not mind using Verilog for your
    > ROMs, you can use $readmemb, $readmemh tasks in an initial block to
    > read the contents of ROM from the file.  This way you can have a
    > portable ROM implementation between FPGA and ASIC versions.  For FPGA
    > version, $readmemb, and $redmemh use the same memory data file as your
    > ASIC foundry's ROM data file.
    >
    > Check and see if Quartus supports $readmemb or $readmemh for
    > synthesis.
    >
    > -- Amal


    Thanks for all the help. I decided to write a little script that
    transforms the output of the assembler into a VHDL array format.

    Works quite well.

    Amal: We have to use Quartus, and VHDL (No Verilog)

    - Walther
     
    Walther, Feb 19, 2009
    #9
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