Using Aggregates in Case Expressions

Discussion in 'VHDL' started by Anand P Paralkar, Oct 27, 2003.

  1. Hi,

    I want to use an aggregate ((en, inp)) as the selector expression of a
    case statement as follows:

    library ieee; use ieee.std_logic_1164.all;

    entity passtrans is
    port (inp, en : in std_logic;
    outp : out std_logic);
    end entity passtrans;

    architecture behav of passtrans is
    begin
    process (inp, en) is
    begin
    case (en, inp) is --**Aggregate used in case selector expression**
    when std_logic_vector'("H1") => outp <= 'H';
    when others => outp <= 'W';
    end case;
    end process;
    end architecture behav;

    However, the compiler returns the following error:

    case expression is not of the correct type

    How do I use an aggregate in the selector expression of a case statement?

    Thanks,
    Anand
     
    Anand P Paralkar, Oct 27, 2003
    #1
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  2. Anand P Paralkar

    MK Guest

    Why you didn't use qualified_expression?

    case std_logic_vector'(en, inp) is

    That's should work ...

    regards,
    MK.
     
    MK, Oct 27, 2003
    #2
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  3. MK,

    Thanks for your reply.

    I have tried using a qualified expression such as std_logic_vector'(en,
    inp), but it does not work.
    The compiler returns an error:

    case expression of this type should have a special form.

    Thanks once again,
    Anand

    MK wrote:

    > Why you didn't use qualified_expression?
    >
    > case std_logic_vector'(en, inp) is
    >
    > That's should work ...
    >
    > regards,
    > MK.
     
    Anand P. Paralkar, Oct 27, 2003
    #3
  4. Anand P Paralkar

    MK Guest

    > I have tried using a qualified expression such as std_logic_vector'(en,
    > inp), but it does not work.
    > The compiler returns an error:
    >
    > case expression of this type should have a special form.


    I've checked it in two well known simulators and it's working! Which
    software you use?

    Other - but of course less readable - way is to declare
    std_logic_vector(1 downto 0) intermediate variable inside this process,
    assign aggregate to this variable, and use this variable in case statement
    instead of aggregate ...

    regards,
    MK.
     
    MK, Oct 27, 2003
    #4
  5. Anand P Paralkar wrote:



    > I want to use an aggregate ((en, inp)) as the selector expression of a
    > case statement as follows:


    > process (inp, en) is
    > begin
    > case (en, inp) is --**Aggregate used in case selector expression**
    > when std_logic_vector'("H1") => outp <= 'H';
    > when others => outp <= 'W';
    > end case;
    > end process;


    Quick'n'dirty:

    process (inp, en) is
    variable dummy : std_ulogic_vector(1 downto 0);
    begin
    dummy:=en & inp;
    case (dummy) is
    when "H1" => outp <= 'H';
    when others => outp <= 'W';
    end case;
    end process;



    Ralf
     
    Ralf Hildebrandt, Oct 27, 2003
    #5
  6. I've found (ModelSim & XST) that it can be very picky about typing of
    case selectors.
    I've come to use an explicit type: that always works. Thus:

    subtype my_sel is std_logic_vector(1 downto 0);
    signal foo, bar : std_logic;
    ...
    process...
    variable cs : my_sel;

    cs := foo & bar;

    case cs is
    when "00" =>

    etc.

    "Anand P. Paralkar" <> wrote:

    :
    :MK,
    :
    :Thanks for your reply.
    :
    :I have tried using a qualified expression such as std_logic_vector'(en,
    :inp), but it does not work.
    :The compiler returns an error:
    :
    : case expression of this type should have a special form.
    :
    :Thanks once again,
    :Anand
    :
    :MK wrote:
    :
    :> Why you didn't use qualified_expression?
    :>
    :> case std_logic_vector'(en, inp) is
    :>
    :> That's should work ...
    :>
    :> regards,
    :> MK.
     
    David R Brooks, Oct 27, 2003
    #6
  7. MK,

    Qualified expression such as std_logic_vector'(en, inp) did not work with
    ncvhdl (a Cadence tool).

    Thanks,
    Anand

    --
    Anand P. Paralkar
    Senior Hardware Engineer
    Ferrari / ADSL / Semiconductors Business Unit
    Sasken Communication Technologies Limited
    139/25, Ring Road, Domlur,
    Bangalore - 560 071
    India
    Email:
    Tel: +91 80 5355501 Extn: 8129
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    On Mon, 27 Oct 2003, MK wrote:

    > > I have tried using a qualified expression such as std_logic_vector'(en,
    > > inp), but it does not work.
    > > The compiler returns an error:
    > >
    > > case expression of this type should have a special form.

    >
    > I've checked it in two well known simulators and it's working! Which
    > software you use?
    >
    > Other - but of course less readable - way is to declare
    > std_logic_vector(1 downto 0) intermediate variable inside this process,
    > assign aggregate to this variable, and use this variable in case statement
    > instead of aggregate ...
    >
    > regards,
    > MK.
    >
    >
    >
     
    Anand P Paralkar, Oct 28, 2003
    #7
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