using multiple ranges

Discussion in 'VHDL' started by paulk, Oct 2, 2009.

  1. paulk

    paulk

    Joined:
    Oct 2, 2009
    Messages:
    1
    Hi..

    I am trying to find an elegant method of concatenating multiple ranges.

    Basically I have a signal

    signal a is std_logic_vector(35 downto 00)
    signal b is std_logic_vector(31 downto 00);

    and I am doing the following remap:

    b <= a(34 downto 27) & a(25 downto 18) & a(16 downto 9) & a(7 downto 0);

    but for readability I would like to replace this statement with something like

    b <= a(BYTE_MAP);

    Does anyone know how to do this? It seems as though I need to define a subtype with multiple ranges.. is this possible?

    ie.

    SUBTYPE BYTE_MAP is range (34 downto 27) & range (25 downto 18) & range....


    Thanks,

    Paul
    paulk, Oct 2, 2009
    #1
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