Renaud said:
Thank for the good words, you made my day ;-)
You're probably right. It could be interesting to compare ac, dc,
leonardo, and others on this.
Actually Mr. Pacalet's function works fine using Leo.
I had a look at the netlist schematic,
and I don't see how it could be done any cleaner.
-- Mike Treseler
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ck_zero is
generic (len : natural := 64);
port (a : in std_ulogic_vector(len-1 downto 0);
clk : in std_ulogic;
rst : in std_ulogic;
zero : out std_ulogic);
end entity ck_zero;
architecture synth of ck_zero is
function ALL_ZERO(V : std_ulogic_vector) return std_ulogic is
-- by Renaud Pacalet
variable T : std_ulogic_vector(V'length - 1 downto 0) := V;
begin
case T'length is
when 0 => return '0';
when 1 => return T(0);
when 2 => return T(0) or T(1);
when others => return
ALL_ZERO(T(T'length - 1 downto T'length / 2))
or ALL_ZERO(T(T'length / 2 - 1 downto 0));
end case;
end ALL_ZERO;
begin
process (rst, clk) is
begin -- process
clked : if rst = '1' then
zero <= '1';
elsif rising_edge(clk) then
zero <= ALL_ZERO(a);
end if clked;
end process;
end architecture synth;
***********************************************
Device Utilization for 2V40cs144
***********************************************
Resource Used Avail Utilization
-----------------------------------------------
IOs 67 88 76.14%
Function Generators 21 512 4.10%
CLB Slices 11 256 4.30%
Dffs or Latches 1 776 0.13%
Block RAMs 0 4 0.00%
Block Multipliers 0 4 0.00%
-----------------------------------------------
Using wire table: xcv2-40-6_wc
Clock Frequency Report
Clock : Frequency
