using signals as registers and initialization

Discussion in 'VHDL' started by rehansherwani, Jul 6, 2008.

  1. rehansherwani

    rehansherwani

    Joined:
    Jun 21, 2008
    Messages:
    2
    hello,
    i am facing problem with initializing signals priority_register_resource4 and priority_register_south4 which im using as registers and only can changed by out side signals PRR4 and PRS4 which are generated by some other code, now i want to initialize priority_register_resource4 and priority_register_south4 as 0 and after that PRR4 and PRS4 will take control of them, obviously i can not initialize them in process because as process ´starts again they becom 0 and value giving by PRR4 and PRS4 will lost which are essantial in my program i tried a way like
    "begin
    a<= '1';
    p: process (rst,clk,PRR4,PRS4)
    begin
    if a = '1' then
    priority_register_resource4 <= '0';
    priority_register_south4 <= '0';
    a <= '0';
    else

    priority_register_resource4 <= PRR4;
    priority_register_south4 <= PRs4;
    end if;"
    but it is not working

    code is given below

    "LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    USE ieee.std_logic_arith.all;

    ENTITY test IS
    port ( clk,rst : in std_logic;
    PRR4 : in std_logic ; --priority register resource signals from lock contoller
    PRS4 : in std_logic ; --priority register south signals from lock contoller
    LRR4 : out std_logic --lock resource register signal for lock controller
    );
    end entity test;
    ARCHITECTURE router OF test IS
    type state_type is (input_to_output_direction,Status_register_resource1);
    signal currentstate_e: state_type;
    signal priority_register_resource4 : std_logic; -- Priority Register Resource
    signal priority_register_south4 : std_logic; -- Priority Register south
    signal a: std_logic;

    begin
    a<= '1';
    p: process (rst,clk,PRR4,PRS4)
    begin
    if a = '1' then
    priority_register_resource4 <= '0';
    priority_register_south4 <= '0';
    a <= '0';
    else

    priority_register_resource4 <= PRR4;
    priority_register_south4 <= PRs4;
    end if;

    if rst = '1' then

    currentstate_e <= input_to_output_direction;
    elsif clk'event and clk = '1' then
    case currentstate_e is
    when input_to_output_direction =>

    if priority_register_resource4 = '1' and priority_register_south4 = '1' then
    currentstate_e <= input_to_output_direction;
    elsif priority_register_resource4 = '1' and priority_register_south4 = '0' then
    currentstate_e <= input_to_output_direction;
    elsif priority_register_resource4= '0' and priority_register_south4= '1' then
    currentstate_e <= status_register_resource1;
    elsif priority_register_resource4= '0' and priority_register_south= '0' then
    currentstate_e <= status_register_resource1;
    end if;
    when Status_register_resource1 =>
    LRR4 <= '1';

    end case;
    end if;
    end process;
    END ARCHITECTURE router;

    i am gratefull of u guys in advance thank you
     
    rehansherwani, Jul 6, 2008
    #1
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