using simulation time in testbench

Discussion in 'VHDL' started by warren_ar, Jan 9, 2008.

  1. warren_ar

    warren_ar

    Joined:
    Jan 9, 2008
    Messages:
    1
    i am writing a testbench that requires me to use the current simulation time in the calculation of when the next event will or should occur, is this possible?

    i know of a workaround by using my own counter in the testbench but i was wondering if this was an alternative, because of the time taken to simulate would be long in cases of high resolution.

    thanks
     
    Last edited: Jan 9, 2008
    warren_ar, Jan 9, 2008
    #1
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