Using SPI core in EDK 9.1

Discussion in 'VHDL' started by AlexQ, Sep 10, 2008.

  1. AlexQ

    AlexQ

    Joined:
    Aug 28, 2008
    Messages:
    1
    Hi,

    I have configured the SPI core like a slave; the master (a PSOC) has a sclk of 1MHz. I changed the code example that there is in C:\EDK\sw\XilinxProcessorIPLib\drivers and used MOSI_I, MISO_O, SCLK_I also SPISEL = Vcc, SS = gnd. I saw the API documentation about the IP but the link XSpi_Config::SlaveOnly has problems. The code is the following:

    Control = 0x2;
    XSpi_mSetControlReg(XPAR_OPB_SPI_0_BASEADDR, Control);
    XSpi_mEnable(XPAR_OPB_SPI_0_BASEADDR);


    while(1)
    {
    NumBytesRcvd = 0;
    while (!(XSpi_mGetStatusReg(XPAR_OPB_SPI_0_BASEADDR) & XSP_SR_RX_EMPTY_MASK) == 0)
    {
    Buffer[NumBytesRcvd++] = XSpi_mRecvByte(XPAR_OPB_SPI_0_BASEADDR);
    xil_printf("%d\t",Buffer[NumBytesRcvd-1]);
    if (NumBytesRcvd == 32) NumBytesRcvd = 0;
    }
    }

    In the hiperterminal only can see zeros. Futhermore, I don't know how configure the frecuency SCLK in the SPI Slave.

    Anyone can help me?

    Thanks
     
    AlexQ, Sep 10, 2008
    #1
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