# Values larger than 32 bit using conv_std_logic_vector

Discussion in 'VHDL' started by Willem Oosthuizen, Jul 1, 2003.

1. ### Willem OosthuizenGuest

signal D is defined as std_logic_vector(51 downto 0)

D <= conv_std_logic_vector(2**n+16#ff#,D'length); only works correctly for
integer n < 31. How can I make it work for integer n < 52 ?

Any suggestions? Why is there this 32 bit limit?

Willem Oosthuizen, Jul 1, 2003

2. ### Alan FitchGuest

"Jon" <> wrote in message
news:...
> "Willem Oosthuizen" <> wrote in message

news:<bdrp4d\$i48\$>...
> > signal D is defined as std_logic_vector(51 downto 0)
> >
> > D <= conv_std_logic_vector(2**n+16#ff#,D'length); only

works correctly for
> > integer n < 31. How can I make it work for integer n <

52 ?
> >
> > Any suggestions? Why is there this 32 bit limit?

>
> Hi Willem,
> VHDL defined the minimum supported range of an integer

to be -2^32
> to (2^31)-1. Some simulators extended the range for

integers and you
> would have to check to see if yours did.
> One way not very efficient is to break up the number

into a sum of
> integers each no greater than 2^32.
>
> jon

I know this is very pedantic but the range is guaranteed
to be
(-2^32)+1 to (2^31)-1, i.e. the most negative number is not
guaranteed by
the standard to be included. Of course in practice is always
is!

Regarding the original question, you might be able to
achieve something
similar using shifts. It's not clear from your original code
if n is a
constant or a signal. I shall assume it's a signal.

process(n)
begin
D <= (others => '0'); -- all bits 0
D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =>
set bit 1
D(7 downto 0) <= X"FF";
end process;

If n is locally static (i.e. a constant), then you *should*
be able to write

D <= (n=> '1', 7 downto 0 => '1', others => '0');

kind regards

Alan

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:

Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views
which are not the
views of Doulos Ltd., unless specifically stated.

Alan Fitch, Jul 2, 2003

3. ### Allan HerrimanGuest

On 1 Jul 2003 08:16:13 -0700, (Jon) wrote:

>"Willem Oosthuizen" <> wrote in message news:<bdrp4d\$i48\$>...
>> signal D is defined as std_logic_vector(51 downto 0)
>>
>> D <= conv_std_logic_vector(2**n+16#ff#,D'length); only works correctly for
>> integer n < 31. How can I make it work for integer n < 52 ?
>>
>> Any suggestions? Why is there this 32 bit limit?

>
>Hi Willem,
> VHDL defined the minimum supported range of an integer to be -2^32
>to (2^31)-1.

Minor correction: the minimum supported range of an integer is
-((2^32)-1) to +((2^32)-1)

Amost all tools do extend the lower range to -(2^32) though.

Regards,
Allan.

Allan Herriman, Jul 2, 2003
4. ### Willem OosthuizenGuest

I said:
D <= conv_std_logic_vector(2**n+16#ff#,D'length);

Alan Said:
> process(n)
> begin
> D <= (others => '0'); -- all bits 0
> D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =>
> set bit 1
> D(7 downto 0) <= X"FF";
> end process;

This is not equivalent. What about the carry when n < 8 ?

"Alan Fitch" <> wrote in message
news:bdu5fd\$6h4\$1\$...
>
> "Jon" <> wrote in message
> news:...
> > "Willem Oosthuizen" <> wrote in message

> news:<bdrp4d\$i48\$>...
> > > signal D is defined as std_logic_vector(51 downto 0)
> > >
> > > D <= conv_std_logic_vector(2**n+16#ff#,D'length); only

> works correctly for
> > > integer n < 31. How can I make it work for integer n <

> 52 ?
> > >
> > > Any suggestions? Why is there this 32 bit limit?

> >
> > Hi Willem,
> > VHDL defined the minimum supported range of an integer

> to be -2^32
> > to (2^31)-1. Some simulators extended the range for

> integers and you
> > would have to check to see if yours did.
> > One way not very efficient is to break up the number

> into a sum of
> > integers each no greater than 2^32.
> >
> > jon

>
> I know this is very pedantic but the range is guaranteed
> to be
> (-2^32)+1 to (2^31)-1, i.e. the most negative number is not
> guaranteed by
> the standard to be included. Of course in practice is always
> is!
>
> Regarding the original question, you might be able to
> achieve something
> similar using shifts. It's not clear from your original code
> if n is a
> constant or a signal. I shall assume it's a signal.
>
> process(n)
> begin
> D <= (others => '0'); -- all bits 0
> D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =>
> set bit 1
> D(7 downto 0) <= X"FF";
> end process;
>
> If n is locally static (i.e. a constant), then you *should*
> be able to write
>
> D <= (n=> '1', 7 downto 0 => '1', others => '0');
>
>
> kind regards
>
> Alan
>
> --
> Alan Fitch
> Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
> Project Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
> Hampshire, BH24 1AW, UK
> Tel: +44 (0)1425 471223 mail:
>
> Fax: +44 (0)1425 471573 Web:
> http://www.doulos.com
>
> The contents of this message may contain personal views
> which are not the
> views of Doulos Ltd., unless specifically stated.
>

Willem Oosthuizen, Jul 2, 2003
5. ### JonGuest

Hi Willem,
All you have to do is what Alan said execpt add 255 to D in places
of directly assigning the lsbs to 255. Using the right packages you
can do 2's complement signed or unsigned using std_logic_vector.

jon

"Willem Oosthuizen" <> wrote in message news:<bdudo2\$bda\$>...
> I said:
> D <= conv_std_logic_vector(2**n+16#ff#,D'length);
>
> Alan Said:
> > process(n)
> > begin
> > D <= (others => '0'); -- all bits 0
> > D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =>
> > set bit 1
> > D(7 downto 0) <= X"FF";
> > end process;

>
> This is not equivalent. What about the carry when n < 8 ?
>
> "Alan Fitch" <> wrote in message
> news:bdu5fd\$6h4\$1\$...
> >
> > "Jon" <> wrote in message
> > news:...
> > > "Willem Oosthuizen" <> wrote in message

> news:<bdrp4d\$i48\$>...
> > > > signal D is defined as std_logic_vector(51 downto 0)
> > > >
> > > > D <= conv_std_logic_vector(2**n+16#ff#,D'length); only

> works correctly for
> > > > integer n < 31. How can I make it work for integer n <

> 52 ?
> > > >
> > > > Any suggestions? Why is there this 32 bit limit?
> > >
> > > Hi Willem,
> > > VHDL defined the minimum supported range of an integer

> to be -2^32
> > > to (2^31)-1. Some simulators extended the range for

> integers and you
> > > would have to check to see if yours did.
> > > One way not very efficient is to break up the number

> into a sum of
> > > integers each no greater than 2^32.
> > >
> > > jon

> >
> > I know this is very pedantic but the range is guaranteed
> > to be
> > (-2^32)+1 to (2^31)-1, i.e. the most negative number is not
> > guaranteed by
> > the standard to be included. Of course in practice is always
> > is!
> >
> > Regarding the original question, you might be able to
> > achieve something
> > similar using shifts. It's not clear from your original code
> > if n is a
> > constant or a signal. I shall assume it's a signal.
> >
> > process(n)
> > begin
> > D <= (others => '0'); -- all bits 0
> > D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1 =>
> > set bit 1
> > D(7 downto 0) <= X"FF";
> > end process;
> >
> > If n is locally static (i.e. a constant), then you *should*
> > be able to write
> >
> > D <= (n=> '1', 7 downto 0 => '1', others => '0');
> >
> >
> > kind regards
> >
> > Alan
> >
> > --
> > Alan Fitch
> > Consultant
> >
> > DOULOS - Developing Design Know-how
> > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
> > Project Services
> >
> > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
> > Hampshire, BH24 1AW, UK
> > Tel: +44 (0)1425 471223 mail:
> >
> > Fax: +44 (0)1425 471573 Web:
> > http://www.doulos.com
> >
> > The contents of this message may contain personal views
> > which are not the
> > views of Doulos Ltd., unless specifically stated.
> >

Jon, Jul 3, 2003
6. ### Alan FitchGuest

"Jon" <> wrote in message
news:...
> Hi Willem,
> All you have to do is what Alan said execpt add 255 to D

in places
> of directly assigning the lsbs to 255. Using the right

packages you
> can do 2's complement signed or unsigned using

std_logic_vector.
>
> jon
>
>
> "Willem Oosthuizen" <> wrote in message

news:<bdudo2\$bda\$>...
> > I said:
> > D <= conv_std_logic_vector(2**n+16#ff#,D'length);
> >
> > Alan Said:
> > > process(n)
> > > begin
> > > D <= (others => '0'); -- all bits 0
> > > D(n) <= '1'); -- e.g. n = 0 => set bit 0, n = 1

=>
> > > set bit 1
> > > D(7 downto 0) <= X"FF";
> > > end process;

> >
> > This is not equivalent. What about the carry when n < 8

?
> >

Sorry, brain failure - luckily Jon has answered it for me!

I must work out how to get outlook express to wrap
sensibly as well...

regards

Alan

--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification *
Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood,
Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:

Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views
which are not the
views of Doulos Ltd., unless specifically stated.

Alan Fitch, Jul 3, 2003

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