Variable bus widths

[Pauly_G2002]

Hi all, hope you are all well.

Anyway I was wondering if anyone can help me with this problem, I have
asked around the office but nobody is sure of an answer.

Basically my problem is this; I have written some code which will take
configuration data in on either one of two mode; either in a parallel
or serial. The problem lies in that if data is read in parallel mode
the data with be 26 bits wide. If the data is written in serial the
data width will be 38 bits wide. So basically I am wondering if there
is a method that will enable me to have a variable output bus width?
I.e 26 bits width when in parallel mode, 38 bits wide in serial.

any help would be fantastic,

Cheers

Paul

 

[KJ]

Hi all, hope you are all well.

Anyway I was wondering if anyone can help me with this problem, I have
asked around the office but nobody is sure of an answer.

Basically my problem is this; I have written some code which will take
configuration data in on either one of two mode; either in a parallel
or serial. The problem lies in that if data is read in parallel mode
the data with be 26 bits wide. If the data is written in serial the
data width will be 38 bits wide. So basically I am wondering if there
is a method that will enable me to have a variable output bus width?
I.e 26 bits width when in parallel mode, 38 bits wide in serial.

any help would be fantastic,

You can do this, if 'mode' is a static constant. Your entity would
then look something like...

entity My_entity is generic(
Mode: std_ulogic);
port(
My_Outputs:
std_ulogic_vector(work.pkg_My_entity.Compute_Num_Bits(Mode) - 1 downto
0));
end My_entity;

where 'Compute_Num_Bits' is a function that would need to be placed in
a package like this...

package pkg_My_entity is
function Compute_Num_Bits(Mode: std_ulogic);
end pkg_My_entity;

package body pkg_My_entity is
function Compute_Num_Bits(Mode: std_ulogic) is
begin
if Mode = '1' then
return(38); -- i.e. 'serial' mode
else
return(26); -- i.e. 'parallel' mode
end if;
end function Compute_Num_Bits;end pkg_My_entity;
end package body pkg_My_entity;

Fair warning: There may be syntax errors in the above code, it's
meant to demonstrate the approach. This code is completely
synthesizable too in case you're wondering.

If 'mode' is not a constant (maybe it's selectable by software or some
other hardware or something) than you can not have a variable bus
width, the entity would have to have the full 38 bits output and you
would have to zero out the appropriate bits based on the mode inside
the architecture.

Kevin Jennings