cltsaig said:
Hi Alan and Jim,
Greatly thanks from your feedback...I kinda perceived the error that I
made on my previous post.
Although, I had an another enigma need you expert/guru's feedback? The
concern is how to reproduce this C function into VHDL?? Is it feasible??
I'd declared a package that defines an floating point array.
void fun(float data[], int nn[], int ndim, int sign)
{
....
}
------- VHDL code --------------------------------
package pack1 is
type array_fp32 is array (positive range <>) of fp32;
end pack1;
use work.pack1.all;
entity fun is
port(
data: in array_fp32 ;
nn: in array_integer;
ndim: in integer;
sign: in integer;
clk:in std_logic;
rst:in std_logic;
result
ut array_fp32
);
end fun;
This should work fine, as long as you have also defined
the array_integer type somwehere.
You can have entities with unconstrained ports, though
not all synthesis tools are happy with them (assuming
of course that you instantatiate a componenent and
bind the ports so that the actual widths are known).
Alternatively you can write a procedure corresponding
to your function. Procedures with unconstrained ports
normally are fine with synthesis tools, if they result
in combinational logic. If they have a clock (as yours
seems to) then some synthesis tools don't like them.
Of course if you're not going to synthesise the code,
don't worry if it's synthesisable or not
regards
Alan
--
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