Variables are showing abnormal values in Time simulation

Discussion in 'VHDL' started by raisul, Oct 6, 2008.

  1. raisul

    raisul

    Joined:
    Sep 23, 2008
    Messages:
    2
    I am new to VHDL and using Quartus II to synthesis my program. My functional simulation is ok but when I am doing time simulation the values of variables : queue_length and x10_queue are showing some values that do not follow my code.

    ---------------------------------------------------------------------------------------------------------------

    if (clk'event and clk='1') then
    if (x10_packet_in/=0) and (x10_packet_in/=prev_packet) and (queue_length/=10) then
    x10_queue(rear):=x10_packet_in;
    prev_packet:=x10_packet_in;
    rear:=rear+1;
    queue_length:=queue_length+1;
    if rear = 10 then
    rear:=0;
    end if;
    end if;

    ----------------------------------------------------------------------------------------------------------------

    Values of queue_length variable should be incremented by 1 each time. But its sequence is like 0-1-2-3-2-7-3-8-5-10 …… .Why it is behaving like this??

    queue_length and rear should be same but its showing difference.

    And sometimes values of x10_queue variable is becoming 0 after inserting a value. I attached the vwf file here.

    Can any one explain this for me? I don’t know what mistake I am doing here. Functional simulation is quite ok. Please help , I am totally stuck here. No way to proceed.

    Thanks in advanced.

    Raisul

    Attached Files:

    Last edited: Oct 6, 2008
    raisul, Oct 6, 2008
    #1
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