Variables Vs signals

Discussion in 'VHDL' started by zingafriend@yahoo.com, Jan 18, 2005.

  1. Guest

    I was wondering what are the advantages and drawbacks on using
    variables as compared to signals in vhdl. I know what they are used to
    model, but are there any specific reasons say as regards to simulation
    etc?
     
    , Jan 18, 2005
    #1
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  2. wrote:
    > I was wondering what are the advantages and drawbacks on using
    > variables as compared to signals in vhdl. I know what they are used to
    > model, but are there any specific reasons say as regards to simulation
    > etc?


    For communication between processes, only signals can be used (not
    considering shared variables here).

    If a signal is only used within a process and not read by any other
    process, it can be replaced by a variable. The advantage is that the
    scope is limited (localized), which in general is a good thing.

    In contrast to signals, the order of reading/assigning variables is
    important. Remember: the value assigned to a signal can be read back
    only after at least a delta cycle. Another way of looking at it (in case
    of a flip-flop): a signal only allows acces to the Q output of a
    flipflop, a variable also makes it possible to read the D input of a
    flipflop.

    Variables allow for a more sequential style of "programming", which can
    be an advantage.

    Finally, when modeling memory (RAM), it is better to use a variable.
    Because variables do not have an event queue associated, their space
    requirement (memory footprint on your workstation/PC) is about ten times
    smaller than the equivalent signal. For large RAMs this could make the
    difference between being able to run, or just thrashing your disk caused
    by swapping.

    Paul.
     
    Paul Uiterlinden, Jan 18, 2005
    #2
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