vcd file generation in ncverilog tool

Discussion in 'VHDL' started by skishor, Oct 31, 2008.

  1. skishor

    skishor

    Joined:
    Oct 31, 2008
    Messages:
    1
    hello,
    can anybody help me out for generating vcd file in ncverilog?
    I have generated that file in verilog code using $dumpfile(myfile.vcd"). Also I have added required $dumpvars, $dumpon, $dumpoff statements. But not able to see the variables in the vcd file. How can I get those veriables in my vcd file? which command is used to simulate and to get timing windows in this tool? I am using < ut & command and able to open the waveform window but not able to get signals in the waveform.

    Regards,
    Sneha
    skishor, Oct 31, 2008
    #1
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