VCS simulation for VHDL DUT and Verilog test bench

Discussion in 'VHDL' started by kartikey, Dec 18, 2007.

  1. kartikey

    kartikey

    Joined:
    Dec 18, 2007
    Messages:
    1
    Likes Received:
    0
    I have VHDL package in file1.vhd. This package is used in DUT file2.vhd. Test bench to test this DUT is developed in verilog (file3.v). I need to simulate it using vcs mix mode simulation. If possible, someone please show me the steps to do the process for vcs-mx.
     
    kartikey, Dec 18, 2007
    #1
    1. Advertisements

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. SneakerNet

    VHDL Test Bench + Help

    SneakerNet, Jan 6, 2005, in forum: VHDL
    Replies:
    3
    Views:
    14,227
    vipinlal
    Mar 3, 2010
  2. john

    simulation and test bench

    john, Mar 26, 2006, in forum: VHDL
    Replies:
    3
    Views:
    2,699
    Andy Peters
    Mar 29, 2006
  3. picnanard
    Replies:
    1
    Views:
    4,157
    picnanard
    Mar 7, 2007
  4. ken.campbell@edgewater.ca

    VHDL Test Bench Package Release

    ken.campbell@edgewater.ca, May 17, 2007, in forum: VHDL
    Replies:
    0
    Views:
    1,284
    ken.campbell@edgewater.ca
    May 17, 2007
  5. Mirza
    Replies:
    11
    Views:
    3,380
    Paul Uiterlinden
    Jul 21, 2007
  6. picnanard
    Replies:
    0
    Views:
    680
    picnanard
    Mar 12, 2009
  7. One Cent
    Replies:
    7
    Views:
    7,264
    ravik
    Sep 10, 2012
  8. priyanka24

    vcs simulation problem

    priyanka24, Feb 19, 2012, in forum: VHDL
    Replies:
    0
    Views:
    1,010
    priyanka24
    Feb 19, 2012
Loading...