VCS simulation for VHDL DUT and Verilog test bench

Discussion in 'VHDL' started by kartikey, Dec 18, 2007.

  1. kartikey

    kartikey

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    Dec 18, 2007
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    I have VHDL package in file1.vhd. This package is used in DUT file2.vhd. Test bench to test this DUT is developed in verilog (file3.v). I need to simulate it using vcs mix mode simulation. If possible, someone please show me the steps to do the process for vcs-mx.
     
    kartikey, Dec 18, 2007
    #1
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