vector concatenation

[pandora]

hello:
I am a beginner of vhdl, I have some knowledge about verilog. please
help me with this problem:
In VHDL serveral vector can concatenate like " a & b & c " also (a ,b
,). i know this can be used as the right operand when assigning. but can
the concatenated vector be the left operand? i writed like this
(a,b,c)<= d ; or
a & & c <= d;
but all can not pass the compilation.

can tell me how the cooncatenated vector be the left operand? thanks
you!!

 

[Niv]

hello:
I am a beginner of vhdl, I have some knowledge about verilog. please
help me with this problem:
In VHDL serveral vector can concatenate like " a & b & c " also (a ,b
,). i know this can be used as the right operand when assigning. but can
the concatenated vector be the left operand? i writed like this
(a,b,c)<= d ; or
a & & c <= d;
but all can not pass the compilation.

can tell me how the cooncatenated vector be the left operand? thanks
you!!

I've not checked, but I don't think you can do this; you have to slice the
rhs thus:

a <= d(msb downto X);
b <= d(X-1 downto Y);
c <= d(Y-1 downto 0);

Or something similar.

Niv.

 

[Egbert Molenkamp]

hello:
I am a beginner of vhdl, I have some knowledge about verilog. please
help me with this problem:
In VHDL serveral vector can concatenate like " a & b & c " also (a ,b
,). i know this can be used as the right operand when assigning. but can
the concatenated vector be the left operand? i writed like this
(a,b,c)<= d ; or
a & & c <= d;
but all can not pass the compilation.

can tell me how the cooncatenated vector be the left operand? thanks
you!!

Here an example. It would be nice if the line marked with --***
could be (co,s)<=...
But that is not allowed (yet).

Egbert Molenkamp

LIBRARY ieee;
USE ieee.numeric_bit.ALL;
ENTITY adder IS
PORT (a,b : IN unsigned(1 DOWNTO 0);
ci : IN bit;
s : OUT unsigned(1 DOWNTO 0);
co : OUT bit);
END adder;
ARCHITECTURE demo OF adder IS
BEGIN
(co,s(1),s(0)) <= ('0'&a) + b + ('0'&ci) ; --***
END demo;

 

[pandora]

but sometimes the left part is an expression, you can not write like this!
so it is really troublesome to write every bit in the left when it is a
very long vector.

 

[Mike Treseler]

(a,b,c)<= d ; or
a & & c <= d;
but all can not pass the compilation.

http://groups.google.com/groups?q=vhdl+aggregate+qualification

-- Mike Treseler

 

[Thomas Stanka]

but sometimes the left part is an expression, you can not write like this!
so it is really troublesome to write every bit in the left when it is a
very long vector.

Then use a variable

my_var:=my_function(x,y,z);
a<=my_var(t downto s);
b<=my_var(s-1 downto r);
c<=my_var(r-1 downto 0);

bye Thomas

 

[ZOLVEZ]

hello

I need some help
I want to do this:

tmp<= tmp1(6 downto 4);

it means I want to use only a part of the vector no all the bits
so I tried to do that, but de ISE of Xilinx doesn't sinthesize it
it reports a message like this:
signal tmp(3 downto 0): is never used

do you know another way ? Please any suggestions to ZOLVEZ@hotm..
thanks a lot

 

[ZOLVEZ]

hello

I need some help
I want to do this:

A<= tmp1(6 downto 4);

it means I want to use only a part of the vector no all the bits
so I tried to do that, but de ISE of Xilinx doesn't sinthesize it
it reports a message like this:
signal tmp1(3 downto 0): is never used

do you know another way ? Please any suggestions to ZOLVEZ@hotm..
thanks a lot

 

[vipinlal]

some examples for concatenation operator is available here..
vhdlguru.blogspot.com/2010/03/concatenation-operator-in-vhdl.html