vector event

Discussion in 'VHDL' started by Matt North, Nov 6, 2003.

  1. Matt North

    Matt North Guest

    Does anyone know of a neat way of knowing when an event has occurred in a
    vector I.e. changed value.
    Their are attributes for this in signals i.e. S'EVENT, S'TRANSACTION etc,
    but these cant be used on arrays. (that's what Leonardo tells me!)

    I basically want to reset a counter when a vector changes its value.
    I am now looking at writing a procedure which periodically compares a
    registered form of the vector with its current state.
    Messy!!

    Thanks,
    Matt
     
    Matt North, Nov 6, 2003
    #1
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  2. Matt North

    VhdlCohen Guest

    >Does anyone know of a neat way of knowing when an event has occurred in a
    >vector I.e. changed value.
    >Their are attributes for this in signals i.e. S'EVENT, S'TRANSACTION etc,
    >but these cant be used on arrays. (that's what Leonardo tells me!)
    >
    >I basically want to reset a counter when a vector changes its value.
    >I am now looking at writing a procedure which periodically compares a
    >registered form of the vector with its current state.
    >Messy!!
    >


    S'event SHOULD work on a vector when any bit of a vector canges value.
    if S'event then ...

    S'transaction should also work on a vector, and the s'transaction is a signal
    of type "bit" that would toggle when an assignment is made.
    wait on S'transaction.

    S'active is like the 'event, except it works on an assignment, even if same
    value is reassigned.
    if s'active.
    So far, this is good for testbench design.

    For synthesis, this is another issue.
    s'event is for a clock, and I don't believe that it would work for synthesis.
    For your counter example, you can do this in a cloked process:
    if (In_vector_reg /= In_vector) then
    counter <= (others => '0');
    ----------------------------------------------------------------------------
    Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
    http://www.vhdlcohen.com/
    Author of following textbooks:
    * Using PSL/SUGAR with Verilog and VHDL
    Guide to Property Specification Language for ABV, 2003 isbn 0-9705394-4-4
    * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    0-9705394-2-8
    * Component Design by Example ", 2001 isbn 0-9705394-0-1
    * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    ------------------------------------------------------------------------------
     
    VhdlCohen, Nov 6, 2003
    #2
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  3. Matt North wrote:

    > I basically want to reset a counter when a vector changes its value.
    > I am now looking at writing a procedure which periodically compares a
    > registered form of the vector with its current state.


    Something like this?

    library ieee;
    use ieee.std_logic_1164.all;

    entity watch is
    port (clk :in std_ulogic;
    reset :in std_ulogic;
    watch_this :in std_logic_vector(7 downto 0);
    change_strobe :eek:ut std_ulogic
    );
    end entity watch;

    architecture synth of watch is --Thu Nov 6 09:56:14 2003 treseler
    begin
    this: process (clk, reset) is
    variable last_watch : std_logic_vector(watch_this'range);
    constant init : std_logic_vector := (watch_this'range => '0');
    begin -- process
    if reset = '1' then
    change_strobe <= '0';
    last_watch := init;
    elsif rising_edge(clk) then
    if watch_this /= last_watch then
    change_strobe <= '1';
    last_watch := watch_this;
    else
    change_strobe <= '0';
    end if;
    end if;
    end process this;

    end architecture synth;

    -- Mike Treseler
     
    Mike Treseler, Nov 6, 2003
    #3
  4. Matt North

    Matt North Guest

    Thanks for your help.

    Matt
     
    Matt North, Nov 10, 2003
    #4
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