Vectors with Opposite Range Directions

Discussion in 'VHDL' started by eliascm, Feb 14, 2011.

  1. eliascm

    eliascm

    Joined:
    Jan 30, 2009
    Messages:
    42
    I had to integrate previously written and tested code into a module where I had to load a std_logic_vector "data" with part of a std_logic_vector "slv_reg0". data and slv_reg0 have opposite range directions. The solution I came up with is shown below. I can't easily simulate this logic since it is part of an embedded design. slv_reg0 is a memory-mapped register that is written to by a Power PC. That part of the logic is handled in a Xilinx supplied template. The part I am concerned about is the process "pdata". Will this work?

    ----------------------------------------------------------------------------------------------------
    -- This logic connects the memory-mapped registers slv_reg0 (used for input to pulse_router) and
    -- slv_reg1 (used as output from pulse router) to pulse_router I/O. Process pdata makes the indices
    -- of data and slv_reg0 match. They are indexed in opposite directions so that using slices will
    -- not work.
    ----------------------------------------------------------------------------------------------------
    pdata : process(data)
    begin
    for i in 0 to data_width - 1 loop
    data(i) <= slv_reg0(i); --input data from slv_reg0
    end loop;
    end process;

    dav <= slv_reg0(data_width); --input dav from slv_reg0
    cmd_code <= slv_reg0(data_width + 1); --input cmd_code from slv_reg0
    busy_n <= slv_reg1(0); --output busy_n is put into slv_reg1(0)
     
    eliascm, Feb 14, 2011
    #1
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