Verification by Non-HDL(C++/Java)??

Discussion in 'VHDL' started by Davy, May 10, 2006.

  1. Davy

    Davy Guest

    Hi all,

    I found that some verification procedure using Non-HDL such as
    C++/Java.

    But how these Non-HDL language generate edge stimulus? Can Non-HDL also
    generate @posedage???

    Is there any basic idea behind it?

    Best regards,
    Davy
     
    Davy, May 10, 2006
    #1
    1. Advertising

  2. Davy

    naren Guest

    Davy wrote:

    > Hi all,
    >
    > I found that some verification procedure using Non-HDL such as
    > C++/Java.
    >
    > But how these Non-HDL language generate edge stimulus? Can Non-HDL also
    > generate @posedage???
    >
    > Is there any basic idea behind it?
    >
    > Best regards,
    > Davy


    Hi Davy,
    They do it through an interface called VHPI (for VHDL) or PLI (for
    verilog). A quick googling should give you decent links.
    You could also write t/b's in perl / python et.al...
    Thanks,
    Naren.
     
    naren, May 10, 2006
    #2
    1. Advertising

  3. Davy

    Hans Guest

    and you might also want to look at SystemC which, IMHO, is easier to
    interface to Verilog/VHDL.

    Hans
    www.ht-lab.com


    "naren" <> wrote in message
    news:...
    >
    > Davy wrote:
    >
    >> Hi all,
    >>
    >> I found that some verification procedure using Non-HDL such as
    >> C++/Java.
    >>
    >> But how these Non-HDL language generate edge stimulus? Can Non-HDL also
    >> generate @posedage???
    >>
    >> Is there any basic idea behind it?
    >>
    >> Best regards,
    >> Davy

    >
    > Hi Davy,
    > They do it through an interface called VHPI (for VHDL) or PLI (for
    > verilog). A quick googling should give you decent links.
    > You could also write t/b's in perl / python et.al...
    > Thanks,
    > Naren.
    >
     
    Hans, May 10, 2006
    #3
  4. Srinivasan Venkataramanan, May 11, 2006
    #4
  5. Davy

    Guest

    Hi Davy,

    I am the creator to teal. Let me know if I can help in any way.

    I am also real close to releasing a verification framework in C++.

    Take Care,
    Mike
     
    , May 11, 2006
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Kieran Francisco

    Timing Diagram to HDL Translation

    Kieran Francisco, Sep 8, 2003, in forum: VHDL
    Replies:
    9
    Views:
    1,362
    VhdlCohen
    Sep 17, 2003
  2. HDL Book Seller

    HDL books for sale

    HDL Book Seller, Sep 30, 2003, in forum: VHDL
    Replies:
    0
    Views:
    578
    HDL Book Seller
    Sep 30, 2003
  3. Alan
    Replies:
    0
    Views:
    536
  4. Guest

    X-HDL

    Guest, Nov 2, 2003, in forum: VHDL
    Replies:
    1
    Views:
    1,521
  5. Evan Lavelle
    Replies:
    10
    Views:
    827
    Mike Treseler
    Apr 26, 2008
Loading...

Share This Page