Eyck Jentzsch said:
Running a so called gatelevel simulation is a common but time consuming
way. For doing this you need a testbench and a simulator. The other way
is using formal verification tools: a static timing analysis tool and an
equivalence checker. But these only verify, that the synthesis step ran
ok, they do not check the functionality of you design.
-Eyck
I have done a hdl level simulation using ModelSim. It all worked
before I even synthesized the design in BuildGates. It has met all my
desired timing, power, and area constraints. It produces a vhdl
netlist like this:
---------snippet-------------------
library ieee;
use ieee.std_logic_1164.all;
entity AWDP_ADD_0 is
port (
add8b_1_stemp: out std_logic_vector(8 downto 0);
R: in std_logic_vector(8 downto 0);
L: in std_logic_vector(8 downto 0)
);
end entity AWDP_ADD_0;
architecture netlist of AWDP_ADD_0 is
signal n_321: std_logic;
signal n_280: std_logic;
signal n_563: std_logic;
signal n_520: std_logic;
signal n_224: std_logic;
signal n_223: std_logic;
signal n_67: std_logic;
signal n_65: std_logic;
signal n_115: std_logic;
signal n_112: std_logic;
signal n_111: std_logic;
signal n_121: std_logic;
signal n_120: std_logic;
signal n_122: std_logic;
signal n_108: std_logic;
signal n_107: std_logic;
signal n_118: std_logic;
signal n_117: std_logic;
signal n_104: std_logic;
signal n_116: std_logic;
signal n_101: std_logic;
component BUFX3 is
port (
A: in std_logic;
Y: out std_logic);
end component BUFX3;
component BUFXL is
port (
A: in std_logic;
Y: out std_logic);
end component BUFXL;
component DLY1X1 is
port (
A: in std_logic;
Y: out std_logic);
end component DLY1X1;
....
....
---------snippet-------------------
There are tons of entities and architectures that it created from my
one top level entity. Custom adders, multipliers, etc.
Ok, maybe I am confused on the symantics of hdl design. What is
verification exactly? Does that mean you are testing the result of
synthesis for functionality? Or, does it simply mean the design does
not violate any DRCs, timing, etc.
Static timing analysis is done in BuildGates, I believe. I get a
detailed report of all the nets and whether or not the arrival times
meet required times. The time difference is reported as 'slack'.
A gate level simulation would check for functionality correct? Our
Cadence does have a VHDL toolbox and it is possible to import a
netlist into a schematic and treat it as a symbol. However, I'm
assuming we would need NC-VHDL installed... Unfortunately I believe we
only have NC-Verilog and Verilog XL :/ I wish I could use one damn
design tool top to bottom so I wouldn't have to be skipping around
like this! GAH
From a research perspective, do you feel it is even necessary to
functionally verify a design? I have plenty of data from synthesis,
including power, critical delay, and area. It would just be nice to
verify that the synthesized design does indeed work as my
pre-synthesis simulation did.
