Verilog Binary Divider

Discussion in 'VHDL' started by Kristo Godari, Nov 4, 2013.

  1. I need a Verilog behavioral model (verilog behavioral code) for:
    - unsigned 8-bit division

    The module I have to use is this one:

    module divider(
    output reg[7:0] q,
    output reg[7:0] r,
    input [7:0] a,b);
    endmodule

    where a=b*q+r

    Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms
    to solve it.

    Can someone help me?
    Kristo Godari, Nov 4, 2013
    #1
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  2. Kristo Godari

    alb Guest

    Hi Kristo,

    On 04/11/2013 15:47, Kristo Godari wrote:
    > I need a Verilog behavioral model (verilog behavioral code) for:
    > - unsigned 8-bit division
    >
    > The module I have to use is this one:
    >
    > module divider(
    > output reg[7:0] q,
    > output reg[7:0] r,
    > input [7:0] a,b);
    > endmodule
    >
    > where a=b*q+r
    >
    > Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms
    > to solve it.
    >
    > Can someone help me?


    why not posting on comp.lang.verilog? this is a vhdl newsgroup.

    About cross-posting I also have some comments: try to avoid it if at all
    possible and if necessary try to mention that you crossposted the
    message on another group so that people might be able to track and post
    accordingly.

    On the particular subject (even if does not make a difference if it is
    verilog or vhdl), I would try to understand what is the peculiarity of
    each algorithm and which of these benefits and costs is more suited to
    your application. Google is your friend here, a first search brings up a
    lot of stuff on power awareness, speed, and also some models (opencores).

    Another possibility is to implement them all and then pick up the one
    that performs better in your particular application. I usually tend to
    use comparison when it comes to performances optimization, but only if
    the gain is worth the pain!

    HTH,

    Al
    alb, Nov 4, 2013
    #2
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  3. Hi Kristo

    Why not assess the offers you have in freelancer? Some offers may guaranteequality work with good quality/$ balance for you.

    Best regards
    Nikolaos Kavvadias

    η ΔευτέÏα, 4 ÎοεμβÏίου 2013 4:47:19 μ.μ. UTC+2, οχÏήστης Kristo Godari έγÏαψε:
    > I need a Verilog behavioral model (verilog behavioral code) for:
    >
    > - unsigned 8-bit division
    >
    >
    >
    > The module I have to use is this one:
    >
    >
    >
    > module divider(
    >
    > output reg[7:0] q,
    >
    > output reg[7:0] r,
    >
    > input [7:0] a,b);
    >
    > endmodule
    >
    >
    >
    > where a=b*q+r
    >
    >
    >
    > Is preferable to use SRT, Newton-Raphson or Goldschmidt algorithms
    >
    > to solve it.
    >
    >
    >
    > Can someone help me?
    Nikolaos Kavvadias, Nov 5, 2013
    #3
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