Verilog Code to VHDL Code

Discussion in 'VHDL' started by pplnet, Dec 9, 2009.

  1. pplnet

    pplnet

    Joined:
    Dec 4, 2009
    Messages:
    4
    Hi all,
    Need experts here helps on this matter

    This is Verilog Code but how to translate into VHDL code?
    Code:
    assign out = (|sum[10:8])?8'hff : sum[7:0];
     
    pplnet, Dec 9, 2009
    #1
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